C8051F411-GMR Silicon Laboratories Inc, C8051F411-GMR Datasheet - Page 166

• Manufacturer Part Number: C8051F411-GMR
• Description: Microcontrollers (MCU) 50 MIPS 32KB 12ADC RTCLOCK 28 PIN MCU
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051F411-GMR

• Processor Series: C8051F4x
• Core: 8051
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2.25 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 20
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F410DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 20 Channel
• On-chip Dac: 12 bit, 2 Channel
• Package: 28QFN EP
• Device Core: 8051
• Family Name: C8051F41x
• Maximum Speed: 50 MHz
• Ram Size: 2.25 KB
• Operating Supply Voltage: 1.8|2.5|3.3|5 V
• Operating Temperature: -40 to 85 °C
• Lead Free Status / Rohs Status: Details

C8051F410/1/2/3
19.1.1. Internal Oscillator Suspend Mode
When software writes a logic 1 to SUSPEND (OSCICN.5), the internal oscillator is suspended. If the sys-
tem clock is derived from the internal oscillator, the input clock to the peripheral or CIP-51 will be stopped
until one of the following events occur:
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When one of the internal oscillator awakening events occur, the internal oscillator, CIP-51, and affected
peripherals resume normal operation, regardless of whether the event also causes an interrupt. The CPU
resumes execution at the instruction following the write to SUSPEND.
166
Port 0 Match Event.
Port 1 Match Event.
Comparator 0 enabled and output is logic 0.
Comparator 1 enabled and output is logic 0.
smaRTClock Oscillator Fail Event.
smaRTClock Alarm Event.
Rev. 1.1