C8051F411-GMR Silicon Laboratories Inc, C8051F411-GMR Datasheet - Page 37
C8051F411-GMR
Manufacturer Part Number
C8051F411-GMR
Description
Microcontrollers (MCU) 50 MIPS 32KB 12ADC RTCLOCK 28 PIN MCU
Manufacturer
Silicon Laboratories Inc
Datasheet
1.C8051F410DK.pdf
(270 pages)
Specifications of C8051F411-GMR
Processor Series
C8051F4x
Core
8051
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
32 KB
Data Ram Size
2.25 KB
Interface Type
I2C, SMBus, SPI, UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
20
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
QFN
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F410DK
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 20 Channel
On-chip Dac
12 bit, 2 Channel
Package
28QFN EP
Device Core
8051
Family Name
C8051F41x
Maximum Speed
50 MHz
Ram Size
2.25 KB
Operating Supply Voltage
1.8|2.5|3.3|5 V
Operating Temperature
-40 to 85 °C
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F411-GMR
Manufacturer:
SiliconL
Quantity:
3 000
Part Number:
C8051F411-GMR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
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Table 3.1. Global DC Electrical Characteristics (Continued)
–40 to +85 °C, 50 MHz System Clock unless otherwise specified. Typical values are given at 25 °C
Digital Supply Current—CPU Active (Normal Mode, fetching instructions from Flash)
Core Supply Current (I
Supply Sensitivity (I
Frequency Sensitivity (I
Notes:
1. For more information on V
2.
3. The Backup Supply Voltage (V
4. SYSCLK is the internal device clock. For operational speeds in excess of 25 MHz, SYSCLK must
5. SYSCLK must be at least 32 kHz to enable debugging.
6. Based on device characterization data, not production tested.
7. Active and Inactive IDD at voltages and frequencies other than those specified can be calculated
8. I
9. Idle IDD can be estimated for frequencies < 1 MHz by simply multiplying the frequency of interest by
VIO must be equal to or greater than VDD.
be derived from the internal clock multiplier.
using the IDD Supply Sensitivity. For example, if the V
I
(2.2 V – 2.0 V) = 5.73 mA at 2.2 V and f = 25 MHz.
frequency sensitivity number for that range. When using these numbers to estimate I
15 MHz, the estimate should be the current at 25 MHz minus the difference in current indicated by
the frequency sensitivity number. For example: V
I
the frequency sensitivity number for that range. When using these numbers to estimate Idle for >
1 MHz, the estimate should be the current at 25 MHz minus the difference in current indicated by
the frequency sensitivity number. For example: V
I
DD
DD
DD
DD
= 5.5 mA typical at 2.0 V and f = 25 MHz. From this, I
can be estimated for frequencies < 15 MHz by simply multiplying the frequency of interest by the
= 5.5 mA – (25 MHz – 20 MHz) x 0.16 mA/MHz = 4.7 mA.
= 2.8 mA – (25 MHz – 5 MHz) x 0.1 mA/MHz = 0.8 mA.
Parameter
DD
)
DD
6,7
DD
)
6
)
6,8
REGIN
RTC-BACKUP
characteristics, see Table 8.1 on page 82.
V
V
V
V
F = 32 kHz
F = 1 MHz
F = 25 MHz
F = 50 MHz
F = 32 kHz
F = 1 MHz
F = 25 MHz
F = 50 MHz
F = 25 MHz
F = 1 MHz
F < 15 MHz, T = 25 ºC
F > 15 MHz, T = 25 ºC
F < 15 MHz, T = 25 ºC
F > 15 MHz, T = 25 ºC
DD
DD
DD
DD
Rev. 1.1
) is used to power the smaRTClock peripheral only.
= 2.0 V:
= 2.5 V:
= 2.0 V:
= 2.5 V:
Conditions
DD
DD
= 2.0 V; F = 20 MHz,
= 2.0 V; F = 5 MHz, Idle
DD
DD
is 2.2 V instead of 2.0 V at 25 MHz:
= 5.5 mA + 1.14 x
C8051F410/1/2/3
Min
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.30
0.43
13.5
0.27
0.16
0.39
Typ
114
100
5.5
9.5
8.3
0.2
13
17
0.65
Max
0.5
6.5
9.5
30
12
40
15
—
—
—
—
—
—
DD
for >
mA/MHz
mA/MHz
mA/MHz
mA/MHz
Units
%/V
%/V
mA
mA
mA
mA
mA
mA
µA
µA
37
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