C8051F411-GMR Silicon Laboratories Inc, C8051F411-GMR Datasheet - Page 28

• Manufacturer Part Number: C8051F411-GMR
• Description: Microcontrollers (MCU) 50 MIPS 32KB 12ADC RTCLOCK 28 PIN MCU
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051F411-GMR

• Processor Series: C8051F4x
• Core: 8051
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2.25 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 20
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F410DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 20 Channel
• On-chip Dac: 12 bit, 2 Channel
• Package: 28QFN EP
• Device Core: 8051
• Family Name: C8051F41x
• Maximum Speed: 50 MHz
• Ram Size: 2.25 KB
• Operating Supply Voltage: 1.8|2.5|3.3|5 V
• Operating Temperature: -40 to 85 °C
• Lead Free Status / Rohs Status: Details

C8051F410/1/2/3
1.4.
The C8051F41x devices have four operating modes: Active (Normal), Idle, Suspend, and Stop. Active
mode occurs during normal operation when the oscillator and peripherals are active. Idle mode halts the
CPU while leaving the peripherals and internal clocks active. Suspend mode halts SYSCLK until a waken-
ing event occurs, which also halts all peripherals using SYSCLK. In Stop mode, the CPU is halted, all inter-
rupts and timers are inactive, and the internal oscillator is stopped. The various operating modes are
described in Table 1.2 below:
See Section
tion “19.1.1. Internal Oscillator Suspend Mode” on page 166
28
Suspend
Active
Stop
Idle
Operating Modes
“10.3. Power Management Modes” on page 101
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
SYSCLK active
CPU active (accessing Flash)
Peripherals active or inactive
depending on user settings
smaRTClock active or inactive
SYSCLK active
CPU inactive (not accessing
Flash)
Peripherals active or inactive
depending on user settings
smaRTClock active or inactive
SYSCLK inactive
CPU inactive (not accessing
Flash)
Peripherals enabled (but not
operating) or disabled depend-
ing on user settings
smaRTClock active or inactive
SYSCLK inactive
CPU inactive (not accessing
Flash)
Digital peripherals inactive;
analog peripherals enabled
(but not operating) or disabled
depending on user settings
smaRTClock inactive
Properties
Table 1.2. Operating Modes Summary
Rev. 1.1
Consumption
Less than Full
Very low
Power
Low
Full
for Idle and Stop mode details. See
for more information on Suspend mode.
(OSCICN.5)
SUSPEND
Entered?
(PCON.0)
(PCON.1)
STOP
IDLE
How
—
event or exter-
nal/MCD reset
How Exited?
Any enabled
device reset
interrupt or
External or
MCD reset
Wakening
—
Sec-