ZLF645S0P2032G Zilog, ZLF645S0P2032G Datasheet - Page 71

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ZLF645S0P2032G

Manufacturer Part Number
ZLF645S0P2032G
Description
Microcontrollers (MCU) 32K Flash 512B RAM 20 pin
Manufacturer
Zilog
Datasheet

Specifications of ZLF645S0P2032G

Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
32 KB
Data Ram Size
512 KB
Interface Type
ICP, UART
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
16
Number Of Timers
3
Maximum Operating Temperature
+ 70 C
Mounting Style
Through Hole
Package / Case
PDIP-20
Minimum Operating Temperature
0 C
Lead Free Status / Rohs Status
 Details
Table 32. TEST Mode Register (TESTMODE)
Exiting ICP Mode
PS026407-0408
Bit Position
[7:3]
[2]
[1:0]
Bits
Field
Reset
R/W
TEST Mode Register
R/W
7
0
The TEST Mode register is used to enable various device test or Flash memory access
modes. At present this register only provides configuration for a single mode where, once
programmed, Flash memory accesses bypass the devices Flash Controller and are done
through the devices I/O pins. A complete description of this mode is available in the Flash
Byte Programming section. This register can only be read or written using the ICP Read/
Write Test Mode Register commands.
The ZLF645 MCU is taken out of ICP mode under any of the following conditions:
Value
Initiating a POR with P36 held High during the entire reset period.
Lowering V
1
0
R
6
0
Description
Reserved — Must be written to 1. Reads return 0.
Flash Controller Bypass Mode
The device is not in Flash Controller Bypass Mode.
The device is in Flash Controller Bypass mode.
Reserved —Must be written to 1. Reads return 0.
DD
Reserved
until the ZLF645 MCU reaches a Voltage Brownout reset state.
R
5
0
R
4
0
R
3
0
Flash Controller
Bypass Mode
R/W
2
0
ZLF645 Series Flash MCUs
Product Specification
R
1
0
Reserved
Exiting ICP Mode
R
0
0
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