ZLF645S0P2032G Zilog, ZLF645S0P2032G Datasheet - Page 78

• Manufacturer Part Number: ZLF645S0P2032G
• Description: Microcontrollers (MCU) 32K Flash 512B RAM 20 pin
• Manufacturer: Zilog

Specifications of ZLF645S0P2032G

• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 512 KB
• Interface Type: ICP, UART
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Package / Case: PDIP-20
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Details

PS026407-0408
Caution:
Page Erase
Mass Erase
The programming operation can only be used to change bits from 1 to 0. To change a
Flash bit (or multiple bits) from 0 to 1 requires execution of either the Page Erase or Mass
Erase commands.
Byte Programming can be accomplished using the In-Circuit Programmer’s Write
Memory command or Z8 LXMC CPU execution of the LDC or LDCI instructions. Refer
to the Z8
instructions. While the Flash Controller programs the Flash memory, the Z8 LXMC CPU
is non-active but the system clock and on-chip peripherals continue to operate. To exit
programming mode and lock the Flash, write any value to the Flash Control register,
except the Mass Erase or Page Erase commands.
The Flash main memory can be erased one page (512 bytes) at a time. Page Erasing the
Flash memory sets all bytes in that page to the value
identifies the page to be erased. Only a page residing in an unprotected sector can be
erased. With the Flash Controller unlocked and the active page set, writing the value
to the Flash Control register initiates the Page Erase operation. While the Flash Controller
executes the Page Erase operation, the Z8 LXMC CPU is non-active but the system clock
and on-chip peripherals continue to operate. The Z8 LXMC CPU resumes operation after
the Page Erase operation completes.
If a Page Erase operation is performed using the ICP, bit 3 of the ICP Status register can be
polled to determine when the operation is complete. When the Page Erase is complete, the
Flash Controller returns to its locked state. You can erase Page 3 of Information Area by
similar procedure, when Flash Page Select register bit 7 is at logic High. See
page 72 for details.
The Flash main memory can also be Mass Erased using the Flash Controller, but only
through the ICP interface and not by the CPU. Mass Erasing the Flash memory sets all
bytes to the value
Flash Control register initiates the Mass Erase operation. If a Mass Erase operation is
performed using the ICP, bit 3 of the ICP Status register can be polled to determine when
the operation is complete. When the Mass Erase is complete, the Flash Controller returns
to its locked state. You cannot mass erase Information Area.
If either of the Flash Memory Protect Option Bits are set as defined in the Flash Op-
tion Bits section, a mass erase of the Flash's main memory must be performed before
Page 3 of the Flash's Information Area can be erased. These two operations must be
done when the device is at operating voltage. That is, if a mass erase is followed with
a power-down then power-up sequence, performing an Information Area Page 3 erase
will not erase its contents.
®
LXMC CPU User Manual (UM0215) for a description of the LDC and LDCI
FFH
. With the Flash Controller unlocked, writing the value
FFH
. The Flash Page Select register
ZLF645 Series Flash MCUs
Product Specification
Flash Controller Operation
Table 35
63H
to the
95H
on
70