ISP1563BMGA ST-Ericsson Inc, ISP1563BMGA Datasheet - Page 18

• Manufacturer Part Number: ISP1563BMGA
• Description: IC USB HOST CTRL HI-SPD 128LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1563BMGA

• Applications: USB Host/Function Processor
• Interface: EHCI Interface
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 128-LQFP
• Mounting Type: Surface Mount
• For Use With: UM10066 - EVAL BRD FOR ISP1563
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISP1563BM-S; ISP1563BM-S

Philips Semiconductors
9397 750 14224
Product data sheet
Table 7:
Bit
15 to 10
9
8
7
6
5
4
3
Symbol
reserved
FBBE
SERRE
SCTRL
PER
VGAPS
MWIE
SC
Command register (address 04h) bit description
Description
-
Fast Back-to-Back Enable: This bit controls whether a master can do
fast back-to-back transactions to various devices. The initialization
software must set this bit if all targets are fast back-to-back capable.
0 — Fast back-to-back transactions are only allowed to the same agent
(value after RST#)
1 — The master is allowed to generate fast back-to-back transactions to
different agents.
SERR# Enable: This bit is an enable bit for the SERR# driver. All devices
that have an SERR# pin must implement this bit. Address parity errors
are reported only if this bit and the PER bit are logic 1.
0 — Disable the SERR# driver
1 — Enable the SERR# driver.
Stepping Control: This bit controls whether a device does address and
data stepping. Devices that never do stepping must clear this bit. Devices
that always do stepping must set this bit. Devices that can do either, must
make this bit read and write, and initialize it to logic 1 after RST#.
Parity Error Response: This bit controls the response of a device to
parity errors. When the bit is set, the device must take its normal action
when a parity error is detected. When the bit is logic 0, the device sets
DPE (bit 15 in the Status register) when an error is detected, but does
not assert PERR# and continues normal operation. The state of this bit
after RST# is logic 0. Devices that check parity must implement this bit.
Devices are required to generate parity, even if parity checking is
disabled.
VGA Palette Snoop: This bit controls how Video Graphics Array (VGA)
compatible and graphics devices handle accesses to VGA palette
registers.
0 — The device should treat palette write accesses like all other
accesses.
1 — Palette snooping is enabled, that is, the device does not respond to
palette register writes and snoops data.
VGA compatible devices should implement this bit.
Memory Write and Invalidate Enable: This is an enable bit for using the
Memory Write and Invalidate command.
0 — Memory Writes must be used instead. State after RST# is logic 0.
1 — Masters may generate the command.
This bit must be implemented by master devices that can generate the
Memory Write and Invalidate command.
Special Cycles: Controls the action of a device on Special Cycle
operations.
0 — Causes the device to ignore all Special Cycle operations. State after
RST# is logic 0.
1 — Allows the device to monitor Special Cycle operations.
Rev. 01 — 14 July 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
HS USB PCI Host Controller
ISP1563
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