ISP1563BMGA ST-Ericsson Inc, ISP1563BMGA Datasheet - Page 52

• Manufacturer Part Number: ISP1563BMGA
• Description: IC USB HOST CTRL HI-SPD 128LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1563BMGA

• Applications: USB Host/Function Processor
• Interface: EHCI Interface
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 128-LQFP
• Mounting Type: Surface Mount
• For Use With: UM10066 - EVAL BRD FOR ISP1563
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISP1563BM-S; ISP1563BM-S

Philips Semiconductors
[1]
Table 66:
Address: Value read from func0 or func1 of address 10h + 30h
9397 750 14224
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
The reserved bits should always be written with the reset value.
HcDoneHead - Host Controller Done Head register bit allocation
11.1.13 HcDoneHead register
R/W
R/W
R/W
R/W
R/W
23
15
31
23
0
0
7
0
0
0
Table 65:
Address: Value read from func0 or func1 of address 10h + 2Ch
The HcDoneHead register contains the physical address of the last completed TD that
was added to the Done queue. In normal operation, the HCD need not read this register
because its content is periodically written to the HCCA.
of the register.
Bit
31 to 4
3 to 0
R/W
R/W
R/W
R/W
R/W
22
14
30
22
0
0
6
0
0
0
Symbol
BCED[27:0] Bulk Current ED: This is advanced to the next ED after the Host
reserved
BCED[3:0]
HcBulkCurrentED - Host Controller Bulk Current Endpoint Descriptor register bit
description
R/W
R/W
R/W
R/W
R/W
21
13
29
21
0
0
5
0
0
0
Description
Controller has served the current ED. The Host Controller continues
processing the list from where it left off in the last frame. When it reaches
the end of the bulk list, the Host Controller checks CLF (bit 1 of
HcCommandStatus). If the CLF bit is not set, nothing is done. If the CLF
bit is set, it copies the content of HcBulkHeadED to HcBulkCurrentED and
clears the CLF bit. The HCD can modify this register only when BLE (bit 5
in the HcControl register) is cleared. When HcControl is set, the HCD
reads the instantaneous value of this register. This is initially set to logic 0
to indicate the end of the bulk list.
-
Rev. 01 — 14 July 2005
R/W
R/W
R/W
R/W
R/W
20
12
28
20
0
0
4
0
0
0
BCED[19:12]
BCED[11:4]
DH[27:20]
DH[19:12]
R/W
R/W
R/W
R/W
R/W
19
11
27
19
0
0
3
0
0
0
Table 66
R/W
R/W
R/W
R/W
R/W
18
10
26
18
0
0
2
0
0
0
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
HS USB PCI Host Controller
reserved
contains the bit allocation
[1]
R/W
R/W
R/W
R/W
R/W
17
25
17
0
9
0
1
0
0
0
ISP1563
R/W
R/W
R/W
R/W
R/W
52 of 107
16
24
16
0
8
0
0
0
0
0