ISP1563BMGA ST-Ericsson Inc, ISP1563BMGA Datasheet - Page 50

• Manufacturer Part Number: ISP1563BMGA
• Description: IC USB HOST CTRL HI-SPD 128LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1563BMGA

• Applications: USB Host/Function Processor
• Interface: EHCI Interface
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 128-LQFP
• Mounting Type: Surface Mount
• For Use With: UM10066 - EVAL BRD FOR ISP1563
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISP1563BM-S; ISP1563BM-S

Philips Semiconductors
Table 60:
Address: Value read from func0 or func1 of address 10h + 24h
9397 750 14224
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcControlCurrentED - Host Controller Control Current Endpoint Descriptor register bit allocation
11.1.10 HcControlCurrentED register
31
23
15
R
R
R
R
0
0
0
7
0
Table 59:
Address: Value read from func0 or func1 of address 10h + 20h
The HcControlCurrentED register contains the physical address of the current ED of the
control list. The bit allocation is given in
Table 61:
Address: Value read from func0 or func1 of address 10h + 24h
Bit
31 to 4
3 to 0
Bit
31 to 4
3 to 0
30
22
14
R
R
R
R
0
0
0
6
0
Symbol
CCED[27:0] Control Current ED: This pointer is advanced to the next ED after serving
reserved
CCED[3:0]
HcControlHeadED - Host Controller Control Head Endpoint Descriptor register bit
description
HcControlCurrentED - Host Controller Control Current Endpoint Descriptor
register bit description
Symbol
CHED[27:0]
reserved
29
21
13
R
R
R
R
0
0
0
5
0
Description
the current ED. The Host Controller needs to continue processing the list
from where it was left in the last frame. When it reaches the end of the
control list, the Host Controller checks CLF (bit 1 of HcCommandStatus). If
set, it copies the content of HcControlHeadED to HcControlCurrentED and
clears the bit. If not set, it does nothing. The HCD is allowed to modify this
register only when CLE (bit 4 of HcControl) is cleared. When set, the HCD
only reads the instantaneous value of this register. Initially, this is set to
logic 0 to indicate the end of the control list.
-
Rev. 01 — 14 July 2005
Description
Control Head ED: The Host Controller traverses the control list,
starting with the HcControlHeadED pointer. The content is loaded
from HCCA during the initialization of the Host Controller.
-
28
20
12
R
R
R
R
0
0
0
4
0
CCED[27:20]
CCED[19:12]
CCED[11:4]
Table
27
19
11
R
R
R
R
0
0
0
3
0
60.
26
18
10
R
R
R
R
0
0
0
2
0
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
HS USB PCI Host Controller
reserved
25
17
R
R
R
R
0
0
9
0
1
0
ISP1563
50 of 107
24
16
R
R
R
R
0
0
8
0
0
0