ISP1563BMGA ST-Ericsson Inc, ISP1563BMGA Datasheet - Page 86

• Manufacturer Part Number: ISP1563BMGA
• Description: IC USB HOST CTRL HI-SPD 128LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1563BMGA

• Applications: USB Host/Function Processor
• Interface: EHCI Interface
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 128-LQFP
• Mounting Type: Surface Mount
• For Use With: UM10066 - EVAL BRD FOR ISP1563
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISP1563BM-S; ISP1563BM-S

Philips Semiconductors
9397 750 14224
Product data sheet
Table 117: PORTSC 1, 2, 3, 4 - Port Status and Control, 1, 2, 3, 4 register bit
Address: Value read from func2 of address 10h + 64h + (4 × Port Number − 1) where Port Number
Bit
11 to 10 LS[1:0]
9
8
7
Symbol
reserved
PR
SUSP
description
Description
Line Status: This field reflects the current logical levels of the DP (bit 11)
and DM (bit 10) signal lines. These bits are used to detect low-speed USB
devices before the port reset and enable sequence. This field is valid only
when the Port Enable bit is logic 0, and the Current Connect Status bit is set
to logic 1.
00b — SE0: Not a low-speed device, perform EHCI reset
01b — K-state: Low-speed device, release ownership of port
10b — J-state: Not a low-speed device, perform EHCI reset
11b — Undefined: Not a low-speed device, perform EHCI reset.
If bit PP is logic 0, this field is undefined.
-
Port Reset: Logic 1 means the port is in reset. Logic 0 means the port is not
in reset. Default = 0. When software sets this bit from logic 0, the bus reset
sequence as defined in Universal Serial Bus Specification Rev. 2.0 is started.
Software clears this bit to terminate the bus reset sequence. Software must
hold this bit at logic 1 until the reset sequence, as specified in Universal
Serial Bus Specification Rev. 2.0 , is completed.
Remark: When software sets this bit, it must also clear the Port Enable bit.
Remark: When software clears this bit, there may be a delay before the bit
status changes to logic 0 because it will not read logic 0 until the reset is
completed. If the port is in high-speed mode after reset is completed, the
Host Controller will automatically enable this port; it can set the Port Enable
bit. A Host Controller must terminate the reset and stabilize the state of the
port within 2 ms of software changing this bit from logic 1 to logic 0. For
example, if the port detects that the attached device is high-speed during a
reset, then the Host Controller must enable the port within 2 ms of software
clearing this bit.
HCH (bit 12 in the USBSTS register) must be logic 0 before software
attempts to use this bit. The Host Controller may hold Port Reset asserted
when the HCH bit is set.
Suspend: Default = 0. Logic 1 means the port is in the suspend state.
Logic 0 means the port is not suspended. The PED (Port Enabled) bit and
this bit define the port states as follows:
PED = 0 and SUSP = X — Port is disabled
PED = 1 and SUSP = 0 — Port is enabled
PED = 1 and SUSP = 1 — port is suspended.
When in the suspend state, downstream propagation of data is blocked on
this port, except for the port reset. If a transaction was in progress when this
bit was set, blocking occurs at the end of the current transaction. In the
suspend state, the port is sensitive to resume detection. The bit status does
not change until the port is suspended and there may be a delay in
suspending a port, if there is a transaction currently in progress on the USB.
Attempts to clear this bit are ignored by the Host Controller. The Host
Controller will unconditionally set this bit to logic 0 when:
If the host software sets this bit when the Port Enabled bit is logic 0, the
results are undefined.
•
•
…continued
Rev. 01 — 14 July 2005
Software changes the FPR (Force Port Resume) bit to logic 0.
Software changes the PR (Port Reset) bit to logic 1.
[1]
[1]
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
HS USB PCI Host Controller
ISP1563
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