ISP1563BMGA ST-Ericsson Inc, ISP1563BMGA Datasheet - Page 48

• Manufacturer Part Number: ISP1563BMGA
• Description: IC USB HOST CTRL HI-SPD 128LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1563BMGA

• Applications: USB Host/Function Processor
• Interface: EHCI Interface
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 128-LQFP
• Mounting Type: Surface Mount
• For Use With: UM10066 - EVAL BRD FOR ISP1563
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISP1563BM-S; ISP1563BM-S

Philips Semiconductors
Table 54:
Address: Value read from func0 or func1 of address 10h + 18h
[1]
Table 56:
Address: Value read from func0 or func1 of address 10h + 1Ch
9397 750 14224
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
The reserved bits should always be written with the reset value.
HcHCCA - Host Controller Communication Area register bit allocation
HcPeriodCurrentED - Host Controller Period Current Endpoint Descriptor register bit allocation
11.1.7 HcHCCA register
11.1.8 HcPeriodCurrentED register
R/W
R/W
R/W
R/W
31
23
15
31
R
0
0
0
7
0
0
The HcHCCA register contains the physical address of the Host Controller
Communication Area (HCCA). The bit allocation is given in
determines the alignment restrictions by writing all 1s to HcHCCA and reading the content
of HcHCCA. The alignment is evaluated by examining the number of zeroes in the lower
order bits. The minimum alignment is 256 B; therefore, bits 0 through 7 will always return
logic 0 when read. This area is used to hold the control structures and the Interrupt table
that are accessed by both the Host Controller and the HCD.
Table 55:
Address: Value read from func0 or func1 of address 10h + 18h
The HcPeriodCurrentED register contains the physical address of the current isochronous
or interrupt ED.
Bit
31 to 8
7 to 0
R/W
R/W
R/W
R/W
30
22
14
30
R
0
0
0
6
0
0
HcHCCA - Host Controller Communication Area register bit description
Symbol
HCCA[23:0]
reserved
Table 56
R/W
R/W
R/W
R/W
29
21
13
29
R
0
0
0
5
0
0
Rev. 01 — 14 July 2005
shows the bit allocation of the register.
Description
Host Controller Communication Area Base Address: This is the
base address of the HCCA.
-
R/W
R/W
R/W
R/W
28
20
12
28
R
0
0
0
4
0
0
HCCA[23:16]
PCED[27:20]
HCCA[15:8]
reserved
HCCA[7:0]
[1]
R/W
R/W
R/W
R/W
27
19
11
27
R
0
0
0
3
0
0
R/W
R/W
R/W
R/W
26
18
10
26
R
0
0
0
2
0
0
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Table
HS USB PCI Host Controller
54. The HCD
R/W
R/W
R/W
R/W
25
17
25
R
0
0
9
0
1
0
0
ISP1563
R/W
R/W
R/W
R/W
48 of 107
24
16
24
R
0
0
8
0
0
0
0