PEF82912FV1.4 Infineon Technologies, PEF82912FV1.4 Datasheet - Page 222

• Manufacturer Part Number: PEF82912FV1.4
• Description: ISDN Interface ISDN
• Manufacturer: Infineon Technologies

Specifications of PEF82912FV1.4

• Mounting Style: SMD/SMT
• Package / Case: MQFP-64
• Lead Free Status / Rohs Status: Details

V
Parameter
Delay for activation
of RSTO
Delay for deactivation
of RSTO
1)
2)
Data Sheet
DD
The Detection Threshold V
Q-SMINT
neither performance and functionality of the Q-SMINT
If the integrated Power-On Reset of the Q-SMINTI is selected (VDDDET = ’0’) and the supply voltage V
ramped up from 0V to 3.3V +/- 5%, then the Q-SMINTI is kept in reset during V
V
already finished start-up. The start-up time of the oscillator circuit is typically in the range between 3ms and
12ms.
DD
= 3.3 V ± 5 %; V
must be ramped up so slowly that the Q-SMINTI leaves the reset state after the oscillator circuit has
®
I. Therefore, the board designer must take into account that a range of voltages is existing, where
SS
DET
= 0 V; T
Symbol
t
t
ACT
DEACT
is far below the specified supply voltage range of analog and digital parts of the
A
= -40 to 85 °C
min.
Limit Values
208
®
typ.
64
I are guaranteed, nor a reset is generated.
max.
10
Electrical Characteristics
Unit Test Condition
µs
ms
DDmin
PEF 82912/82913
< V
DD
< V
2001-03-30
DET
+ V
DD
Hys
is
.