PEF82912FV1.4 Infineon Technologies, PEF82912FV1.4 Datasheet - Page 50
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PEF82912FV1.4
Manufacturer Part Number
PEF82912FV1.4
Description
ISDN Interface ISDN
Manufacturer
Infineon Technologies
Datasheet
1.PEF82912FV1.4.pdf
(240 pages)
Specifications of PEF82912FV1.4
Mounting Style
SMD/SMT
Package / Case
MQFP-64
Lead Free Status / Rohs Status
Details
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Manufacturer:
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PEF82912FV1.4
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Monitoring Data
Figure 16
simultaneously. For monitoring on DU and/or DD the channel registers with even
numbers (CDA10, CDA20) are assigned to time slots with even numbers TS(2n) and the
channel registers with odd numbers (CDA11, CDA21) are assigned to time slots with odd
numbers TS(2n+1). The user has to take care of this restriction by programming the
appropriate time slots.
This mode is only valid if two blocks (e.g. both transceivers) are programmed to these
timeslots and communicating via IOM -2.
However, if only one block is programmed to this timeslot the timeslots for CDAx0 and
CDAx1 can be programmed completely independently.
•.
Figure 16
Data Sheet
a) Monitoring Data
gives an example for monitoring of two IOM -2 time slots each on DU or DD
Example for Monitoring Data
CDA_CR1.
CDA_CR2.
EN_O:
EN_O:
EN_I:
EN_I:
DPS:
DPS:
TSS:
TSS:
CDA20
CDA10
TS(2n)
TS(2n)
’0’
’1’
’0’
’1’
’1’
’0’
36
TS(2n+1)
TS(2n+1)
CDA11
CDA21
’0’
’1’
’0’
’1’
’1’
’0’
Functional Description
PEF 82912/82913
DD
DU
2001-03-30
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