PEF82912FV1.4 Infineon Technologies, PEF82912FV1.4 Datasheet - Page 40

• Manufacturer Part Number: PEF82912FV1.4
• Description: ISDN Interface ISDN
• Manufacturer: Infineon Technologies

Specifications of PEF82912FV1.4

• Mounting Style: SMD/SMT
• Package / Case: MQFP-64
• Lead Free Status / Rohs Status: Details

The internal reset sources set the MODE1 register to its reset value.
Table 8
1)
•
• C/I Code Change (Exchange Awake)
• Watchdog Timer
After the selection of the watchdog timer (RSS = ’11’) an internal timer is reset and
started. During every time period of 128 ms the microcontroller has to program the
WTC1- and WTC2 bits in the following sequence to reset and restart the watchdog timer:
Otherwise the timer expires and a WOV-interrupt (ISTA Register) together with a reset
out pulse on pin RSTO of 125 µs is generated.
Deactivation of the watchdog timer is only possible with a hardware reset (including
expiration of the watchdog timer).
As in the SCOUT-S, the watchdog timer is clocked with the IOM -2 clocks and works
only if the internal IOM -2 clocks are active. Hence, the power consumption is
minimized in state power down.
Software Reset Register (SRES)
Several main functional blocks of the Q-SMINT I can be reset separately by software
setting the corresponding bit in the SRES register. This is equivalent to a hardware reset
of the corresponding functional block. The reset state is activated as long as the bit is set
to ’1’.
Data Sheet
POR/UVD can be enabled/disabled via pin VDDDET
A change in the downstream C/I channel (C/I0) generates a reset pulse of 125 µs
RSS2
Bit 1
250 µs.
0
0
1
1
RSS1
Reset Source Selection
Bit 0
1.
2.
0
1
0
1
WTC1
1
0
C/I Code
Change
--
--
x
/RSTO disabled (= high impedance)
WTC2
0
1
26
Watchdog
Timer
--
--
x
Functional Description
PEF 82912/82913
POR/UVD
RST
x
x
x
2001-03-30
1)
and
t