PEF82912FV1.4 Infineon Technologies, PEF82912FV1.4 Datasheet - Page 63

• Manufacturer Part Number: PEF82912FV1.4
• Description: ISDN Interface ISDN
• Manufacturer: Infineon Technologies

Specifications of PEF82912FV1.4

• Mounting Style: SMD/SMT
• Package / Case: MQFP-64
• Lead Free Status / Rohs Status: Details

•
DU 1st byte value
DU 2nd byte value
DU 3rd byte value
DU 4th byte value
DU (nth + 3) byte value
All registers can be read back when setting the R/W bit to ’1’. The Q-SMINT I responds
by sending his IOM -2 specific address byte (81
Note: Application Hint:
2.3.3.5
To prevent lock-up situations in a MONITOR transmission a time-out procedure can be
enabled by setting the time-out bit (TOUT) in the MONITOR configuration register
(MCONF). An internal timer is always started when the transmitter must wait for the reply
of the addressed device or for transmit data from the microcontroller. After 40 IOM -2
frames (5 ms) without reply the timer expires and the transmission will be aborted with
an EOM (End of Message) command by setting the MX bit to ’1’ for two consecutive
IOM -2 frames.
2.3.3.6
Figure 24
Receive interrupt status MDR has two enable bits, MONITOR Receive interrupt Enable
(MRE) and MR bit Control (MRC). The MONITOR channel End of Reception MER,
MONITOR channel Data Acknowledged MDA and MONITOR channel Data Abort MAB
interrupt status bits have a common enable bit MONITOR Interrupt Enable MIE.
MRE set to “0” prevents the occurrence of MDR status, including when the first byte of
a packet is received. When MRE is set to “1” but MRC is set to “0”, the MDR interrupt
status is generated only for the first byte of a receive packet. When both MRE and MRC
are set to “1”, MDR is always generated and all received MONITOR bytes - marked by
a 1-to-0 transition in MX bit - are stored. Additionally, a MRC set to “1” enables the control
of the MR handshake bit according to the MONITOR channel protocol.
Data Sheet
It is not allowed to disable the MX- and MR-control in the programming device at
the same time! First, the MX-control must be disabled, then the µC has to wait for
an End of Reception before the MR-control may be disabled. Otherwise, the Q-
SMINT I does not recognize an End of Reception.
shows the interrupt structure of the MONITOR handler. The MONITOR Data
Monitor Time-Out Procedure
MONITOR Interrupt Logic
R/W
1
0
0
49
Header Byte
Register Address
h
0
Data 1
Data n
) followed by the requested data.
Command/
0
0
Functional Description
PEF 82912/82913
0
1
2001-03-30