TXC-06412BROG Transwitch Corporation, TXC-06412BROG Datasheet - Page 134

• Manufacturer Part Number: TXC-06412BROG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06412BROG

• Lead Free Status / Rohs Status: Compliant

PHAST-12P Device
DATA SHEET
TXC-06412B
PRELIMINARY TXC-06412B-MB, Ed. 2
June 2005
11.10 HIGH ORDER POH PORT INTERFACE
The transmit POH port interface allows insertion of the POH bytes.
All received High Order POH bytes are output on the receive High Order POH port interface.
Each interface consists of clock, data, data enable, address and address enable lines.
The address is an 8-bit word with following format:
The least significant nibble identifies the POH byte on the High Order POH Port Interface:
The most significant nibble identifies the High Order path number:
Note the address corresponding to the master VC is used for concatenated structures. E.g.,
when mapping four VC-4/STS-3c’s SPE in a STM-4/OC-12, only 0x0, 0x3, 0x6 and 0x9 will
be valid values for A[7:4].
-
High Order Pointer Tracking, Retiming and Pointer Generation
A7
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A6
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A7
High Order path number
A3
0
0
0
0
0
0
0
0
1
A5
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A6
A4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
A2
0
0
0
0
1
1
1
1
0
A5
VC-3/STS-1 SPE #1 or VC-4/STS-3c SPE #1
VC-3/STS-1 SPE #2
VC-3/STS-1 SPE #3
VC-3/STS-1 SPE #4 or VC-4/STS-3c SPE #2
VC-3/STS-1 SPE #5
VC-3/STS-1 SPE #6
VC-3/STS-1 SPE #7 or VC-4/STS-3c SPE #3
VC-3/STS-1 SPE #8
VC-3/STS-1 SPE #9
VC-3/STS-1 SPE #10 or VC-4/STS-3c SPE #4
VC-3/STS-1 SPE #11
VC-3/STS-1 SPE #12
NA
NA
NA
NA
A4
A1
0
0
1
1
0
0
1
1
0
A3
POH byte identification
A0
0
1
0
1
0
1
0
1
0
A2
Assigned to
POH Byte
A1
-
B3
C2
G1
H4
K3
N1
F2
F3
J1
A0
1 3 4 o f 2 26