TXC-06412BROG Transwitch Corporation, TXC-06412BROG Datasheet - Page 135

• Manufacturer Part Number: TXC-06412BROG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06412BROG

• Lead Free Status / Rohs Status: Compliant

1 3 5 o f 2 26
11.10.1 Transmit High Order POH Port Interface
11.10.2 Receive High Order POH Port Interface
The transmit High Order POH port interface allows inserting most High Order Path Overhead
bytes into the High Order POH. J1 and C2 cannot be selected from the transmit High Order
POH port interface, while the B3 BIP-8 can be used as error mask on the calculated BIP-8 for
test purposes.
The Transmit POH Port consists of following leads:
The Transmit POH Port protocol is as follows (see
Note: No configuration is necessary for the Transmit POH Port. The source of the POH bytes
can be configured in the memory map of the POH Generator (see
All received High Order Path Overhead bytes are sent over a serial Receive POH Port
interface. The values sent out on this interface are the raw, unprocessed values, except for
B3, where an error mask is calculated (ones indicates the errored bits).
The Receive POH Port consists of following leads:
The Receive POH Port protocol is as follows (see
Note: No configuration is necessary for this POH Port.
• Output Transmit POH Port Clock POHTXCLK
• Output Transmit POH Port Address Latch Enable POHTXALE
• Output Transmit POH Port Address POHTXADDR
• Output Transmit POH Port Data Latch Enable POHTXDLE
• Input Transmit TOH Port Data POHTXDATA
• Output Receive POH Port Clock POHRXCLK
• Output Receive POH Port Address Latch Enable POHRXALE
• Output Receive POH Port Address POHRXADDR
• Output Receive POH Port Data Latch Enable POHRXDLE
• Output Receive POH Port Data POHRXDATA
1. The 8-bit address for the requested byte is output on POHTXADDR, most significant
2. A one cycle gap is left open.
3. The Data Latch Enable POHTXDLE is asserted and the 8-bit data word is sampled
1. The 8-bit address for the transmitted byte is output on POHRXADDR, most signifi-
2. A one cycle gap is left open.
3. The 8-bit data of the transmitted TPOH byte is output on POHRXDATA. During this
- High Order Pointer Tracking, Retiming and Pointer Generation -
bit first. During this time the Address Latch Enable POHTXALE is asserted.
on the input POHTXDATA, most significant bit first.
cant bit first. During this time the Address Latch Enable POHRXALE is asserted.
time the Data Latch Enable POHRXDLE is asserted.
Figure
Figure
7):
8):
PRELIMINARY TXC-06412B-MB, Ed. 2
Table
PHAST-12P Device
88).
DATA SHEET
TXC-06412B
June 2005