TXC-06412BROG Transwitch Corporation, TXC-06412BROG Datasheet - Page 214

• Manufacturer Part Number: TXC-06412BROG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06412BROG

• Lead Free Status / Rohs Status: Compliant

PHAST-12P Device
DATA SHEET
TXC-06412B
PRELIMINARY TXC-06412B-MB, Ed. 2
June 2005
0x00A0 BytesConfig
0x00A2
Offset
0x0000 ModeTTIConfig
0x0002
0x0084
Offset
0x0000
0x0200
0x0300
0x0400
12.22 POH MONITOR
0
1
2
3
4
5
6
3 - 0
4
6 - 5
10 - 7
Bits
Bits
Bypass
AIS_Force
Unidirectional
TTI_ExTiMessage
TTI_ExTi64
TTI_TimEnable
TIM_AIS_Insert_Disable
ExpectedBytes
B3_Config
G1_AcceptNoOfIntervals
G1_CountBitErrors
Reserved
Reserved
CorrDefects_Mask
VC_Config
Common_Config
Common_Status
VC_Status
Name
Table 89: POH Monitor Path Configuration
Name
Table 88: POH Monitor
-
Memory Maps and Bit Descriptions
All 0x0 T_VCXPM_ExpectedBytes
Init
Init
0x0 No processing is done on this high order path when 0x1.
0x0 AIS insertion is forced when 0x1.
0x0 Enables the uni-directional option when 0x1. When the uni-directional option is
0x0 Ignore expected TTI message and assume non-specific repeating byte message
0x0 64 byte trace message when 0x1, 16 byte trace message when 0x0. This setting
0x0 TIM detection is enabled when 0x1.
0x0 AIS insertion on Trail Trace Identifier Mismatch defect is disabled when 0x1.
0x5 Integer 3, 5 (ETSI) or 10 (Telcordia)
0x0 REI bit errors are reported when 0x1, block errors when 0x0.
0x0 Reserved.
0x5 Reserved.
Use this bypass for unused paths.
active, the FarEndBlockErrorCounter will report 0 and the RDI defect is cleared.
when 0x0. When 0x1 the TTI message has to match the specified expected
message (16 or 64 byte TTI message).
is only valid when TTI_ExTiMessage is 0x1.
Expected bytes.
T_BIP_Detector_Config
Configuration for B3 BIP detector (DEG/EXC).
Number of consecutive frames to debounce G1.
T_VCXPM_Defects
Correlated defects mask.
rw
rw
ro/cow_1
ro/cow_1
Access
T_VCXPM_Config
High order path configuration.
The high order path to be configured is selected by indirect
access. See the Config_Channel register in the
Common_Config record to select the desired high order path.
T_VCXPM_Common_Config
General configuration.
T_VCXPM_Common_Status
General status.
Note: Latched bits are clear-on-write-1, all others are read-only.
Array (12) of T_VCXPM_Status
Offset between two elements = 0x40.
Array index indicates the high order path.
High order path status.
Note: Latched bits are clear-on-write-1, all others are read-only.
(T_VC_POH_MONITOR)
(See page
(See page
(See page
-
(T_VCXPM_Config)
216.)
Description
(See page
215.)
215.)
Description
(See page
(See page
214.)
(See page
218.)
216.)
218.)
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