TXC-06412BROG Transwitch Corporation, TXC-06412BROG Datasheet - Page 171

• Manufacturer Part Number: TXC-06412BROG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06412BROG

• Lead Free Status / Rohs Status: Compliant

1 7 1 o f 2 26
Offset
Offset
0x000C 7 - 0
0x000A 7 - 0
0x000E 7 - 0
0x0000 11 - 0
0x0004
0x0006 0
0x0008 0
12.5 INTERRUPT
Bits
Bits
APS_Interrupts_Mask
IntCtrl_Config
HINT
HINTEN
RxLine2_Reset
RxLine3_Reset
RxLine4_Reset
Name
Name
- Memory Maps and Bit Descriptions -
Table 6: Reset Generator
Table 7: Interrupt
Init
0x0 rw
0x0 rw
0x0 rw
Init
0xFFF rw
0x0 ro
0x0 rw
Access
rw
Access
Microprocessor Controller Reset for Rx Line 2. Writing the value
0x91 to this register generates a reset in the Receive Line 2
clock domain.
Reset is active as long as this register contains the value 0x91.
Note: Only assert reset when RESETH = 0x91. Can be
deasserted at any time.
Microprocessor Controller Reset for Rx Line 3. Writing the value
0x91 to this register generates a reset in the Receive Line 3
clock domain.
Reset is active as long as this register contains the value 0x91.
Note: Only assert reset when RESETH = 0x91. Can be
deasserted at any time.
Microprocessor Controller Reset for Rx Line 4. Writing the value
0x91 to this register generates a reset in the Receive Line 4
clock domain.
Reset is active as long as this register contains the value 0x91.
Note: Only assert reset when RESETH = 0x91. Can be
deasserted at any time.
(T_INTERRUPT)
APS Interrupts Mask.
See APS_Interrupts register for details.
T_InterruptCtrl_Config
Interrupt and performance configuration.
Global device interrupt (HINT = Hardware INTerrupt).
The global device interrupt is enabled when 0x1, no
interrupt will be generated when 0x0 (HINTEN =
Hardware INTerrupt ENable).
(T_RGEN)
PRELIMINARY TXC-06412B-MB, Ed. 2
Description
Description
(See page
PHAST-12P Device
172.)
DATA SHEET
TXC-06412B
June 2005