GC80960RD66 Intel, GC80960RD66 Datasheet - Page 13

• Manufacturer Part Number: GC80960RD66
• Manufacturer: Intel

Specifications of GC80960RD66

• Family Name: i960 RX
• Device Core: 80960
• Device Core Size: 32b
• Frequency (max): 66MHz
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 95C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 352
• Package Type: HLBGA
• Lead Free Status / Rohs Status: Not Compliant

2.2.1
2.2.2
2.2.3
Datasheet
Burst Bus
A 32-bit high-performance bus controller interfaces the 80960RX to external memory and
peripherals. The Bus Control Unit fetches instructions and transfers data on the local bus
at the rate of up to four 32-bit words per six clock cycles. The external address/data bus is
multiplexed.
Users may configure the 80960RX bus controller to match the fundamental memory
organization of an application. Physical bus width is programmable for up to eight regions.
Data caching is programmed through a group of logical memory templates and a defaults
register. The Bus Control Unit features include:
Three-deep load/store queue decouples the bus from the 80960 core
Upon reset, the 80960RX conducts an internal self test. Before executing its first
instruction, it performs an external bus confidence test by performing a checksum on the
first words of the Initialization Boot Record.
Timer Unit
The timer unit (TU) contains two independent 32-bit timers that are capable of counting at
several clock rates and generating interrupts. Each is programmed by use of the Timer
Unit registers. These memory-mapped registers are addressable on 32-bit boundaries.
The timers have a single-shot mode and auto-reload capabilities for continuous operation.
Each timer has an independent interrupt request to the 80960RX interrupt controller. The
TU can generate a fault when unauthorized writes from user mode are detected.
Priority Interrupt Controller
Low interrupt latency is critical to many embedded applications. As part of its highly flexible
interrupt mechanism, the 80960RX exploits several techniques to minimize latency:
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Multiplexed external bus minimizes pin count
32-, 16- and 8-bit bus widths simplify I/O interfaces
External ready control for address-to-data, data-to-data and data-to-next-address wait
state types
Little endian byte ordering
Unaligned bus accesses performed transparently
Interrupt vectors and interrupt handler routines can be reserved on-chip
Register frames for high-priority interrupt handlers can be cached on-chip
The interrupt stack can be placed in cacheable memory space
Intel
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i960
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RX I/O Processor at 3.3 Volts
Functional Overview
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