GC80960RD66 Intel, GC80960RD66 Datasheet - Page 5

• Manufacturer Part Number: GC80960RD66
• Manufacturer: Intel

Specifications of GC80960RD66

• Family Name: i960 RX
• Device Core: 80960
• Device Core Size: 32b
• Frequency (max): 66MHz
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 95C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 352
• Package Type: HLBGA
• Lead Free Status / Rohs Status: Not Compliant

Figures
Datasheet
1
2
3
4
5
6
7
8
9
10 T
11 T
12 T
13 T
14 DT/R# and DEN# Timings Waveform......................................................................................... 57
15 I
16 Fast Page-Mode Read Access, Non-Interleaved, 2,1,1,1 Wait State, 32-Bit 80960 Local Bus..59
17 Fast Page-Mode Write Access, Non-Interleaved, 2,1,1,1 Wait States, 32-Bit 80960 Local Bus 60
18 FPM DRAM System Read Access, Interleaved, 2,0,0,0 Wait States ......................................... 61
19 FPM DRAM System Write Access, Interleaved, 1,0,0,0 Wait States ......................................... 62
20 EDO DRAM, Read Cycle............................................................................................................63
21 EDO DRAM, Write Cycle ............................................................................................................ 63
22 BEDO DRAM, Read Cycle ......................................................................................................... 64
23 BEDO DRAM, Write Cycle.......................................................................................................... 64
24 32-Bit Bus, SRAM Read Accesses with 0 Wait States ............................................................... 65
25 32-Bit Bus, SRAM Write Accesses with 0 Wait States ............................................................... 65
26 Non-Burst Read and Write Transactions without Wait States, 32-Bit 80960 Local Bus ............. 66
27 Burst Read and Write Transactions without Wait States, 32-Bit 80960 Local Bus .....................67
28 Burst Write Transactions with 2,1,1,1 Wait States, 32-Bit 80960 Local Bus .............................. 68
29 Burst Read and Write Transactions without Wait States, 8-Bit 80960 Local Bus....................... 69
30 Burst Read and Write Transactions with 1, 0 Wait States and Extra Tr State on Read,
31 Bus Transactions Generated by Double Word Read Bus Request, Misaligned One Byte
32 HOLD/HOLDA Waveform For Bus Arbitration ............................................................................ 72
33 80960 Core Cold Reset Waveform............................................................................................. 73
34 80960 Local Bus Warm Reset Waveform................................................................................... 74
Product Name Functional Block Diagram..................................................................................... 9
80960JF Core Block Diagram..................................................................................................... 12
352L HL-PBGA Package Diagram (Top and Side View)............................................................ 30
352L HL-PBGA Package Diagram (Bottom View)...................................................................... 31
Thermocouple Attachment - No Heat Sink ................................................................................. 40
Thermocouple Attachment - With Heat Sink............................................................................... 41
VCC5 Current-Limiting Resistor .................................................................................................45
AC Test Load.............................................................................................................................. 55
S_CLK, TCLK Waveform............................................................................................................55
16-Bit 80960 Local Bus...............................................................................................................70
From Quad Word Boundary, 32-Bit 80960 Local Bus ................................................................ 71
2
OV
OF
IS
LXL
C Interface Signal Timings ....................................................................................................... 58
and T
Output Float Waveform ....................................................................................................... 56
Output Delay Waveform ...................................................................................................... 55
and T
IH
LXA
Input Setup and Hold Waveform..............................................................................56
Relative Timings Waveform................................................................................ 57
Intel
®
i960
®
RX I/O Processor at 3.3 Volts
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