GC80960RD66 Intel, GC80960RD66 Datasheet - Page 22

• Manufacturer Part Number: GC80960RD66
• Manufacturer: Intel

Specifications of GC80960RD66

• Family Name: i960 RX
• Device Core: 80960
• Device Core Size: 32b
• Frequency (max): 66MHz
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 95C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 352
• Package Type: HLBGA
• Lead Free Status / Rohs Status: Not Compliant

Intel
Package Information
Table 5.
22
®
i960
®
RX I/O Processor at 3.3 Volts
Power Requirement, Processor Control and Test Signal Descriptions
VCCPLL3:
L_RST#
STEST
TRST#
Name
FAIL#
V
TCK
TDO
TMS
N.C.
V
V
TDI
CC5
CC
SS
1
Type
H(Q)
R(Q)
H(Q)
P(Q)
R(0)
S(L)
S(L)
S(L)
A(L)
O
O
O
–
–
–
–
I
I
I
I
I
I
FAIL indicates a failure of the processor built-in self-test performed during
initialization. FAIL# is asserted immediately upon reset and toggles during self-test
to indicate the status of individual tests:
0 = Self Test Failed
1 = Self Test Passed
LOCAL BUS RESET notifies external devices that the local bus has reset.
SELF TEST enables or disables the processor internal self-test feature at
initialization. STEST is examined at the end of P_RST#. When STEST is asserted,
the processor performs its internal self-test and the external bus confidence test.
When STEST is deasserted, the processor performs only the external bus
confidence test.
0 = Self Test Disabled
1 = Self Test Enabled
TEST CLOCK is a CPU input that provides the clocking function for IEEE 1149.1
Boundary Scan Testing (JTAG). State information and data are clocked into the
processor on the rising edge; data is clocked out of the processor on the falling
edge.
TEST DATA INPUT is the serial input signal for JTAG. TDI is sampled on the rising
edge of TCK, during the SHIFT-IR and SHIFT-DR states of the Test Access Port.
This signal has a weak internal pullup which is active during reset to ensure normal
operation when the signal is not connected.
TEST DATA OUTPUT is the serial output signal for JTAG. TDO is driven on the
falling edge of TCK during the SHIFT-IR and SHIFT-DR states of the Test Access
Port. At other times, TDO floats.
TEST MODE SELECT is sampled at the rising edge of TCK to select the operation
of the test logic for IEEE 1149.1 Boundary Scan testing. This signal has a weak
internal pullup which is active during reset to ensure normal operation when the
signal is not connected.
TEST RESET asynchronously resets the Test Access Port (TAP) controller function
of IEEE 1149.1 Boundary Scan testing (JTAG). When using the Boundary Scan
feature, connect a pulldown resistor (1.5 K ) between this signal and V
TAP is not used, this signal must be connected to V
required. The signal has a weak internal pullup which must be overcome during
reset to ensure normal operation.
POWER. Connect to a 3.3 Volt V
5 VOLT REFERENCE VOLTAGE. Input is the reference voltage for the 5 V-tolerant
I/O buffers. Connect this signal to +5 V for use with signals which exceed 3.3 V.
When all inputs are from 3.3 V components, connect this signal to 3.3 V.
GROUND. Connect to a V
NO CONNECT. Do not make electrical connections to these balls.
PLL POWER. For external connection to a 3.3 V V
requires external filtering.
• When self-test passes, the processor deasserts FAIL# and commences
• When self-test fails, the processor asserts FAIL# and then stops executing.
operation from user code.
Self-test failing does not cause the bridge to stop execution.
SS
board plane.
CC
Description
board plane.
CC
SS
; however, no resistor is
board plane. Power to PLLs
SS
Datasheet
. When