GC80960RD66 Intel, GC80960RD66 Datasheet - Page 52

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GC80960RD66

Manufacturer Part Number
GC80960RD66
Description
Manufacturer
Intel
Datasheet

Specifications of GC80960RD66

Family Name
i960 RX
Device Core
80960
Device Core Size
32b
Frequency (max)
66MHz
Supply Voltage 1 (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Operating Temp Range
0C to 95C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
352
Package Type
HLBGA
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
GC80960RD66
Manufacturer:
INTEL
Quantity:
20 000
Intel
Electrical Specifictions
Table 27.
Table 28.
4.4.3
Table 29.
52
®
i960
®
RX I/O Processor at 3.3 Volts
BEDO DRAM Output Timings (Sheet 2 of 2)
SRAM/ROM Output Timings
Boundary Scan Test Signal Timings
Boundary Scan Test Signal Timings (Sheet 1 of 2)
T
T
NOTES:
T
T
T
T
T
NOTES:
T
T
T
T
T
T
T
T
T
T
NOTES:
1. Signal generated on the rising edge of an internally generated 2XCLK which corresponds to the center of
2. Output switching between V
1. Signal generated on the rising edge of an internally generated 2XCLK which corresponds to the center of
2. Output switching between V
Symbol
1. Not tested.
2. Outputs precharged to V
Symbol
OV38
OV39
OV40
OV41
OV42
OV43
OV44
BSF
BSCH
BSCL
BSCR
BSCF
BSIS1
BSIH1
BSOV1
BSOF1
BSOV2
an S_CLK period. For testing purposes, the signal is specified relative to the rising edge of S_CLK with the
0.5Tc period offset.
an S_CLK period. For testing purposes, the signal is specified relative to the rising edge of S_CLK with
the 0.5Tc period offset.
MA11:0 Output Valid Delay - Column Address Write Cycles
DWE1:0# Rising and Falling Edge Output Valid Delay
CE1:0# Rising and Falling Edge Output Valid
Delay
MWE3:0# Rising Edge Output Valid Delay
MWE3:0# Falling Edge Output Valid Delay
MA11:0 Output Valid Delay - Initial Address
MA11:0 Output Valid Delay - Burst Address
TCK Frequency
TCK High Time
TCK Low Time
TCK Rise Time
TCK Fall Time
Input Setup to TCK — TDI,
TMS
Input Hold from TCK — TDI,
TMS
TDO Valid Delay
TDO Float Delay
All Outputs (Non-Test) Valid
Delay
Parameter
CC5
Description
CC3
CC3
maximium.
maximium and V
maximium and V
Min
15
15
0
4
6
3
3
3
SS
SS
0.5T
Max
30
30
30
.
.
5
5
F
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.5Tc +1
0.5Tc +2
Min
2
1
2
Measured at 1.5 V (1)
Measured at 1.5 V (1)
0.8 V to 2.0 V (1)
2.0 V to 0.8 V (1)
Relative to falling edge of TCK (2)
Relative to falling edge of TCK (2)
Relative to falling edge of TCK (2)
2
2
0.5Tc +10
0.5Tc +9
Max
10
8
9
10
11
Notes
Units
ns
ns
ns
ns
ns
ns
ns
Datasheet
2
2
2
2
1,2
2
2
Notes

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