PI7C8150BND Pericom Semiconductor, PI7C8150BND Datasheet - Page 11

PI7C8150BND

Manufacturer Part Number
PI7C8150BND
Description
Manufacturer
Pericom Semiconductor
Datasheet

Specifications of PI7C8150BND

Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Operating Temperature (max)
85C
Package Type
BGA
Rad Hardened
No
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PI7C8150BND
Quantity:
800
Part Number:
PI7C8150BNDE
Manufacturer:
CYPRESS
Quantity:
101
Part Number:
PI7C8150BNDE
Manufacturer:
Pericom
Quantity:
10 000
Part Number:
PI7C8150BNDE
Manufacturer:
ALTERA
0
Part Number:
PI7C8150BNDE
Manufacturer:
PERICOM
Quantity:
20 000
Part Number:
PI7C8150BNDI
Quantity:
8 239
Part Number:
PI7C8150BNDIE
Manufacturer:
PERICOM
Quantity:
300
Part Number:
PI7C8150BNDIE
Manufacturer:
PERICOM
Quantity:
301
Part Number:
PI7C8150BNDIE
Manufacturer:
Pericom
Quantity:
10 000
Part Number:
PI7C8150BNDIE
Manufacturer:
PERICOM
Quantity:
20 000
1
INTRODUCTION
Product Description
The PI7C8150 is Pericom Semiconductor’s third-generation PCI-PCI Bridge.
It is designed to be fully compliant with the 32-bit, 66MHz implementation of
the PCI Local Bus Specification, Revision 2.2. The PI7C8150 supports only synchronous
bus transactions between devices on the Primary Bus running at 33MHz to 66MHz and the
Secondary Buses operating at either 33MHz or 66MHz. The Primary and Secondary Bus
can also operate in concurrent mode, resulting in added increase in system performance.
Concurrent bus operation off-loads and isolates unnecessary traffic from the Primary Bus,
thereby enabling a master and a target device on the Secondary PCI Bus to communicate
even while the Primary Bus is busy.
Product Features
32-bit Primary and Secondary Ports run up to 66MHz
Compliant with the PCI Local Bus Specification, Revision 2.2
Compliant with PCI-to-PCI Bridge Architecture Specification, Revision 1.1.
Compliant with the Advanced Configuration Power Interface (ACPI) Specification.
Compliant with the PCI Power Management Specification, Revision 1.0.
Concurrent Primary to Secondary Bus operation and independent intra-Secondary Port
channel to reduce traffic on the Primary Port
Provides internal arbitration for one set of nine secondary bus masters
Supports posted write buffers in all directions
Two 128 byte FIFO’s for delay transactions
Two 128 byte FIFO’s for posted memory transactions
Enhanced address decoding
Interrupt handling
Supports system transaction ordering rules
Extended commercial temperature range 0°C to 85°C
IEEE 1149.1 JTAG interface support
3.3V core; 3.3V and 5V signaling
208-pin FQFP package
- All I/O and memory commands
- Type 1 to Type 0 configuration conversion
- Type 1 to Type 1 configuration forwarding
- Type 1 configuration write to special cycle conversion
- Programmable 2-level priority arbiter
- Disable control for use of external arbiter
- 32-bit I/O address range
- 32-bit memory-mapped I/O address range
- VGA addressing and VGA palette snooping
- ISA-aware mode for legacy support in the first 64KB of I/O address range
- PCI interrupts are routed through an external interrupt concentrator
1
March 19, 2003 – Revision 1.04
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
PI7C8150

Related parts for PI7C8150BND