PI7C8150BND Pericom Semiconductor, PI7C8150BND Datasheet - Page 6

• Manufacturer Part Number: PI7C8150BND
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150BND

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

13
14
13.1
13.2
14.1
14.1.1
14.1.2
14.1.3
14.1.4
14.1.5
14.1.6
14.1.7
14.1.8
14.1.9
14.1.10
14.1.11
14.1.12
14.1.13
14.1.14
14.1.15
14.1.16
14.1.17
14.1.18
14.1.19
14.1.20
14.1.21
OFFSET 28h ....................................................................................................................................... 69
14.1.22
OFFSET 2Ch....................................................................................................................................... 69
14.1.23
14.1.24
14.1.25
14.1.26
14.1.27
14.1.28
14.1.29
14.1.30
14.1.31
14.1.32
14.1.33
4Ch
14.1.34
14.1.35
14.1.36
14.1.37
58h
14.1.38
14.1.39
14.1.40
14.1.41
14.1.42
SUPPORTED COMMANDS......................................................................................................... 60
CONFIGURATION REGISTERS................................................................................................ 62
PRIMARY INTERFACE ............................................................................................................. 60
SECONDARY INTERFACE ....................................................................................................... 61
CONFIGURATION REGISTER.................................................................................................. 62
VENDOR ID REGISTER – OFFSET 00h......................................................................... 63
DEVICE ID REGISTER – OFFSET 00h .......................................................................... 63
COMMAND REGISTER – OFFSET 04h.......................................................................... 63
STATUS REGISTER – OFFSET 04h ................................................................................ 64
REVISION ID REGISTER – OFFSET 08h ...................................................................... 65
CLASS CODE REGISTER – OFFSET 08h....................................................................... 65
CACHE LINE SIZE REGISTER – OFFSET 0Ch ............................................................ 65
PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch ........................................... 66
HEADER TYPE REGISTER – OFFSET 0Ch................................................................... 66
PRIMARY BUS NUMBER REGISTSER – OFFSET 18h............................................ 66
SECONDARY BUS NUMBER REGISTER – OFFSET 18h ........................................ 66
SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h.................................... 66
SECONDARY LATENCY TIMER REGISTER – OFFSET 18h .................................. 66
I/O BASE REGISTER – OFFSET 1Ch.......................................................................... 67
I/O LIMIT REGISTER – OFFSET 1Ch ........................................................................ 67
SECONDARY STATUS REGISTER – OFFSET 1Ch................................................... 67
MEMORY BASE REGISTER – OFFSET 20h .............................................................. 68
MEMORY LIMIT REGISTER – OFFSET 20h............................................................. 68
PEFETCHABLE MEMORY BASE REGISTER – OFFSET 24h ................................ 68
PREFETCHABLE MEMORY LIMIT REGISTER – OFFSET 24h ............................ 69
PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS REGISTER –
PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS REGISTER –
I/O BASE ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h .......................... 69
I/O LIMIT ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h......................... 70
ECP POINTER REGISTER – OFFSET 34h................................................................. 70
INTERRUPT LINE REGISTER – OFFSET 3Ch ......................................................... 70
INTERRUPT PIN REGISTER – OFFSET 3Ch............................................................ 70
BRIDGE CONTROL REGISTER – OFFSET 3Ch ....................................................... 70
DIAGNOSTIC / CHIP CONTROL REGISTER – OFFSET 40h.................................. 72
ARBITER CONTROL REGISTER – OFFSET 40h...................................................... 73
EXTENDED CHIP CONTROL REGISTER – OFFSET 48h....................................... 73
UPSTREAM MEMORY CONTROL REGISTER – OFFSET 48h ............................... 74
SECONDARY BUS ARBITER PREEMPTION CONTROL REGISTER – OFFSET
UPSTREAM (S TO P) MEMORY BASE REGISTER – OFFSET 50h ........................ 74
UPSTREAM (S TO P) MEMORY LIMIT REGISTER – OFFSET 50h....................... 74
UPSTREAM (S TO P) MEMORY BASE UPPER 32-BITS REGISTER – OFFSET 54h
UPSTREAM (S TO P) MEMORY LIMIT UPPER 32-BITS REGISTER – OFFSET
P_SERR_L EVENT DISABLE REGISTER – OFFSET 64h........................................ 75
GPIO DATA AND CONTROL REGISTER – OFFSET 64h ........................................ 76
SECONDARY CLOCK CONTROL REGISTER – OFFSET 68h ................................. 77
P_SERR_L STATUS REGISTER – OFFSET 68h ........................................................ 77
PORT OPTION REGISTER – OFFSET 74h ................................................................ 78
.......................................................................................................................................... 74
.......................................................................................................................................... 75
.......................................................................................................................................... 75
vi
March 19, 2003 – Revision 1.04
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
PI7C8150