MAX1243BCSA Maxim Integrated Products, MAX1243BCSA Datasheet - Page 16

• Manufacturer Part Number: MAX1243BCSA
• Description: ADC (A/D Converters) Integrated Circuits (ICs)
• Manufacturer: Maxim Integrated Products

Specifications of MAX1243BCSA

• Number Of Adc Inputs: 1
• Architecture: SAR
• Conversion Rate: 73 KSPs
• Resolution: 10 bit
• Input Type: Voltage
• Interface Type: 3-Wire (SPI, QSPI, Microwire)
• Voltage Reference: External
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 2.7 V
• Maximum Power Dissipation: 471 mW
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: SO-8
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: No

12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
16
MAX1221
15, 23,
16–19
32, 33
24, 25
9–12,
1, 2
13
14
20
21
22
—
—
—
3
4
5
6
7
8
______________________________________________________________________________________
MAX1223 MAX1343
2, 15, 24,
16–19
9–12,
PIN
—
—
13
14
32
—
20
21
22
—
1
3
4
5
6
7
8
15, 23,
32, 33
16–19
24, 25
9–12
1, 2
13
14
20
21
22
—
—
3
4
5
6
7
8
GPIOC0, GPIOC1 General-Purpose I/O C0, C1. GPIOC0, C1 can sink 4mA and source 2mA.
GPIOA0, GPIOA1 General-Purpose I/O A0, A1. GPIOA0, A1 can sink and source 15mA.
CNVST/AIN11
OUT0–OUT3
OUT0–OUT7
RES_SEL
AGND
NAME
DGND
DOUT
LDAC
DV
SCLK
AV
EOC
N.C.
D.C.
DIN
CS
DD
DD
Active-Low Conversion-Start Input/Analog Input 11. See Table 5 for details
on programming the setup register.
Active-Low End-of-Conversion Output. Data is valid after the falling edge
of EOC.
Digital Positive-Power Input. Bypass DV
capacitor.
Digital Ground. Connect DGND to AGND.
Serial-Data Output. Data is clocked out on the falling edge of the SCLK
clock in modes 00, 01, and 10. Data is clocked out on the rising edge of
the SCLK clock in mode 11. It is high impedance when CS is high.
Serial-Clock Input. Clocks data in and out of the serial interface. (Duty
cycle must be 40% to 60%). See Table 5 for details on programming the
clock mode.
Serial-Data Input. DIN data is latched into the serial interface on the falling
edge of SCLK.
DAC Outputs
DAC Outputs
Positive Analog Power Input. Bypass AV
capacitor.
Analog Ground
No Connection. Not internally connected.
Do Not Connect. Do not connect to this pin.
Active-Low Load DAC. LDAC is an asynchronous active-low input that
updates the DAC outputs. Drive LDAC low to make the DAC registers
transparent.
Active-Low Chip-Select Input. When CS is low, the serial interface is
enabled. When CS is high, DOUT is high impedance.
Reset Select. Select DAC wake-up mode. Set RES_SEL low to wake up
the DAC outputs with a 100kΩ resistor to GND or set RES_SEL high to
wake up the DAC outputs with a 100kΩ resistor to V
external V
REF
.
FUNCTION
DD
DD
to DGND with a 0.1µF
to AGND with a 0.1µF
Pin Description
REF
. The default is the