MAX1243BCSA Maxim Integrated Products, MAX1243BCSA Datasheet - Page 34

• Manufacturer Part Number: MAX1243BCSA
• Description: ADC (A/D Converters) Integrated Circuits (ICs)
• Manufacturer: Maxim Integrated Products

Specifications of MAX1243BCSA

• Number Of Adc Inputs: 1
• Architecture: SAR
• Conversion Rate: 73 KSPs
• Resolution: 10 bit
• Input Type: Voltage
• Interface Type: 3-Wire (SPI, QSPI, Microwire)
• Voltage Reference: External
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 2.7 V
• Maximum Power Dissipation: 471 mW
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: SO-8
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: No

12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
In clock mode 00, the wake-up, acquisition, conversion,
and shutdown sequence is initiated through CNVST
and performed automatically using the internal oscilla-
tor. Results are added to the internal FIFO to be read
out later. See Figure 6 for clock mode 00 timing after a
command byte is issued. See Table 5 for details on
programming the clock mode in the setup register.
Initiate a scan by setting CNVST low for at least 40ns
before pulling it high again. The MAX1221/MAX1223/
MAX1343 then wake up, scan all requested channels,
Figure 6. Clock Mode 00—After writing a command byte, set CNVST low for at least 40ns to begin a conversion.
Figure 7. Clock Mode 01—After writing a command byte, request multiple conversions by setting CNVST low for each conversion.
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CNVST
DOUT
SCLK
CNVST
EOC
DOUT
SCLK
CS
EOC
CS
(ACQUISITION 1)
(CONVERSION 1)
Internally Timed Acquisitions and
Applications Information
ADC Conversions in Clock Mode 00
t
DOV
Conversions Using CNVST
(ACQUISITION 2)
t
CSW
(UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS)
t
RDS
(CONVERSION 2)
MSB1
MSB1
store the results in the FIFO, and shut down. After the
scan is complete, EOC is pulled low and the results are
available in the FIFO. Wait until EOC goes low before
pulling CS low to communicate with the serial interface.
EOC stays low until CS or CNVST is pulled low again. A
temperature-conversion result, if requested, precedes
all other FIFO results.
Do not issue a second CNVST signal before EOC goes
low; otherwise, the FIFO can be corrupted. Wait until all
conversions are complete before reading the FIFO. SPI
communications to the DAC and GPIO registers are per-
mitted during conversion. However, coupled noise may
result in degraded ADC signal-to-noise ratio (SNR).
LSB1
LSB1
MSB2
MSB2