MAX1243BCSA Maxim Integrated Products, MAX1243BCSA Datasheet - Page 20

• Manufacturer Part Number: MAX1243BCSA
• Description: ADC (A/D Converters) Integrated Circuits (ICs)
• Manufacturer: Maxim Integrated Products

Specifications of MAX1243BCSA

• Number Of Adc Inputs: 1
• Architecture: SAR
• Conversion Rate: 73 KSPs
• Resolution: 10 bit
• Input Type: Voltage
• Interface Type: 3-Wire (SPI, QSPI, Microwire)
• Voltage Reference: External
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 2.7 V
• Maximum Power Dissipation: 471 mW
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: SO-8
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: No

12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Table 1. Command Byte (MSB First)
The MAX1221/MAX1223/MAX1343 power up with all
blocks in shutdown (including the reference). All regis-
ters power up in state 00000000, except for the setup
register and the DAC input register. The setup register
powers up at 0010 1000 with CKSEL1 = 1 and REF-
SEL1 = 1. The DAC input register powers up to FFFh
when RES_SEL is high and powers up to 000h when
RES_SEL is low.
The MAX1221/MAX1223/MAX1343 ADCs use a fully dif-
ferential successive-approximation register (SAR) con-
version technique and on-chip track-and-hold (T/H)
circuitry to convert temperature and voltage signals into
12-bit digital results. The analog inputs accept both sin-
gle-ended and differential input signals. Single-ended
signals are converted using a unipolar transfer function,
and differential signals are converted using a selec-
table bipolar or unipolar transfer function. See the ADC
Transfer Functions section for more data.
When addressing the setup, register bits 5 and 4 of the
command byte (CKSEL1 and CKSEL0, respectively)
control the ADC clock modes. See Table 5. Choose
between four different clock modes for various ways to
start a conversion and determine whether the acquisi-
tions are internally or externally timed. Select clock
mode 00 to configure CNVST/AIN_ to act as a conver-
sion start and use it to request internally timed conver-
sions, without tying up the serial bus. In clock mode 01,
use CNVST to request conversions one channel at a
time, thereby controlling the sampling speed without
tying up the serial bus. Request and start internally
X = Don’t care.
* Only applicable on the MAX1221/MAX1343.
20
Conversion
Setup
ADC Averaging
DAC Select
Reset
GPIO Configure*
GPIO Write*
GPIO Read*
No Operation
REGISTER NAME
______________________________________________________________________________________
BIT 7
1
0
0
0
0
0
0
0
0
Power-Up Default State
CHSEL3
BIT 6
ADC Clock Modes
1
0
0
0
0
0
0
0
12-Bit ADC
CHSEL2
CKSEL1
BIT 5
1
0
0
0
0
0
0
CHSEL1
CKSEL0
AVGON
BIT 4
timed conversions through the serial interface by writ-
ing to the conversion register in the default clock mode,
10. Use clock mode 11 with SCLK up to 3.6MHz for
externally timed acquisitions to achieve sampling rates
up to 225ksps. Clock mode 11 disables scanning and
averaging. See Figures 6–9 for timing specifications on
how to begin a conversion.
These devices feature an active-low, end-of-conversion
output. EOC goes low when the ADC completes the last
requested operation and is waiting for the next com-
mand byte. EOC goes high when CS or CNVST go low.
EOC is always high in clock mode 11.
The MAX1221/MAX1223/MAX1343 use a fully differen-
tial ADC for all conversions. When a pair of inputs are
connected as a differential pair, each input is connect-
ed to the ADC. When configured in single-ended mode,
the positive input is the single-ended channel and the
negative input is referred to AGND. See Figure 2.
In differential mode, the T/H samples the difference
between two analog inputs, eliminating common-mode
DC offsets and noise. IN+ and IN- are selected from the
following pairs: AIN0/AIN1, AIN2/AIN3, AIN4/AIN5,
AIN6/AIN7, AIN8/AIN9, AIN10/AIN11. AIN0–AIN7 are
available on all devices. AIN0–AIN11 are available on
the MAX1223. See Tables 5–8 for more details on con-
figuring the inputs. For the inputs that are configurable
as CNVST, REF2, and an analog input, only one func-
tion can be used at a time.
Address the unipolar- and bipolar-mode registers
through the setup register (bits 1 and 0). See Table 5 for
1
0
0
0
0
0
REFSEL1
CHSEL0
NAVG1
BIT 3
Single-Ended or Differential Conversions
X
1
0
0
0
0
Unipolar or Bipolar Conversions
REFSEL0
SCAN1
NAVG0
RESET
BIT 2
X
0
0
0
0
DIFFSEL1
NSCAN1
SCAN0
SLOW
BIT 1
X
1
1
0
0
DIFFSEL0
NSCAN0
FBGON
TEMP
BIT 0
X
1
0
1
0