MAX1243BCSA Maxim Integrated Products, MAX1243BCSA Datasheet - Page 21

• Manufacturer Part Number: MAX1243BCSA
• Description: ADC (A/D Converters) Integrated Circuits (ICs)
• Manufacturer: Maxim Integrated Products

Specifications of MAX1243BCSA

• Number Of Adc Inputs: 1
• Architecture: SAR
• Conversion Rate: 73 KSPs
• Resolution: 10 bit
• Input Type: Voltage
• Interface Type: 3-Wire (SPI, QSPI, Microwire)
• Voltage Reference: External
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 2.7 V
• Maximum Power Dissipation: 471 mW
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: SO-8
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: No

the setup register. See Figures 3 and 4 for the transfer-
function graphs. Program a pair of analog inputs for dif-
ferential operation by writing a one to the appropriate bit
of the bipolar- or unipolar-mode register. Unipolar mode
sets the differential input range from 0 to V
tive differential analog input in unipolar mode causes the
digital output code to be zero. Selecting bipolar mode
sets the differential input range to ±V
output code is binary in unipolar mode and two’s com-
plement in bipolar mode.
In single-ended mode, the MAX1221/MAX1223/
MAX1343 always operate in unipolar mode. The analog
inputs are internally referenced to AGND with a full-scale
input range from 0 to the selected reference voltage.
The equivalent circuit of Figure 2 shows the ADC input
architecture of the MAX1223. In track mode, a positive
input capacitor is connected to AIN0–AIN11 in single-
ended mode and AIN0, AIN2, AIN4–AIN10 in differential
mode. A negative input capacitor is connected to AGND
in single-ended mode or AIN1, AIN3, AIN5–AIN11 in dif-
ferential mode. The MAX1221/MAX1343 feature eight
analog input channels (AIN0–AIN7). In track mode, a pos-
itive input capacitor is connected to AIN0–AIN7 in single-
ended mode and to AIN0, AIN2, AIN4, and AIN6 in
differential mode. A negative input capacitor is connected
to AGND in single-ended mode or to AIN1, AIN3, AIN5,
and AIN7 in differential mode. For external T/H timing, use
clock mode 01. After the T/H enters hold mode, the differ-
ence between the sampled positive and negative input
Figure 2. MAX1223 Equivalent Input Circuit
(SINGLE-ENDED),
(SINGLE-ENDED),
(DIFFERENTIAL)
(DIFFERENTIAL)
AIN0–AIN11
AIN4–AIN10
AIN5–AIN11
AIN0, AIN2,
AIN1, AIN3,
AGND
12-Bit, Multichannel ADCs/DACs with FIFO,
HOLD
ACQ
ACQ
______________________________________________________________________________________
AV
HOLD
DD
Temperature Sensing, and GPIO Ports
AGND
/ 2
REF1
CIN+
CIN-
DAC
ACQ
Analog Input (T/H)
REF1
/ 2. The digital
REF1.
COMPARATOR
A nega-
HOLD
voltages is converted. The input capacitance charging
rate determines the time required for the T/H to acquire
an input signal. If the input signal’s source impedance is
high, the required acquisition time lengthens.
Any source impedance below 300Ω does not signifi-
cantly affect the ADC’s AC performance. A high-imped-
ance source can be accommodated either by
lengthening t
a 1µF capacitor between the positive and negative ana-
log inputs. The combination of the analog-input source
impedance and the capacitance at the analog input cre-
ates an RC filter that limits the analog input bandwidth.
The ADC’s input-tracking circuitry has a 1MHz small-sig-
nal bandwidth, making it possible to digitize high-speed
transient events and measure periodic signals with
bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. Anti-alias prefiltering
of the input signals is necessary to avoid high-frequency
signals aliasing into the frequency band of interest.
Internal electrostatic-discharge (ESD) protection diodes
clamp all analog inputs to AV
the inputs to swing from (AGND - 0.3V) to (AV
0.3V) without damage. However, for accurate conver-
sions near full scale, the inputs must not exceed AV
by more than 50mV or be lower than AGND by 50mV. If
an analog input voltage exceeds the supplies, limit the
input current to 2mA.
The MAX1221/MAX1223/MAX1343 contain a first-
in/first-out (FIFO) buffer that holds up to 16 ADC results
plus one temperature result. The internal FIFO allows
the ADC to process and store multiple internally
clocked conversions and a temperature measurement
without being serviced by the serial bus.
If the FIFO is filled and further conversions are request-
ed without reading from the FIFO, the oldest ADC
results are overwritten by the new ADC results. Each
result contains 2 bytes, with the MSB preceded by four
leading zeros. After each falling edge of CS, the oldest
available pair of bytes of data is available at DOUT,
MSB first. When the FIFO is empty, DOUT is zero.
The first 2 bytes of data read out after a temperature
measurement always contain the 12-bit temperature
result, preceded by four leading zeros, MSB first. If anoth-
er temperature measurement is performed before the first
temperature result is read out, the old measurement is
overwritten by the new result. Temperature results are in
degrees Celsius (two’s complement), at a resolution of 8
ACQ
(only in clock mode 01) or by placing
Analog Input Protection
DD
and AGND, allowing
Input Bandwidth
Internal FIFO
DD
DD
21
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