MAX1243BCSA Maxim Integrated Products, MAX1243BCSA Datasheet - Page 36

• Manufacturer Part Number: MAX1243BCSA
• Description: ADC (A/D Converters) Integrated Circuits (ICs)
• Manufacturer: Maxim Integrated Products

Specifications of MAX1243BCSA

• Number Of Adc Inputs: 1
• Architecture: SAR
• Conversion Rate: 73 KSPs
• Resolution: 10 bit
• Input Type: Voltage
• Interface Type: 3-Wire (SPI, QSPI, Microwire)
• Voltage Reference: External
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 2.7 V
• Maximum Power Dissipation: 471 mW
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: SO-8
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: No

12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
In clock mode 10, the wake-up, acquisition, conversion,
and shutdown sequence is initiated by writing a com-
mand byte to the conversion register, and is performed
automatically using the internal oscillator. This is the
default clock mode upon power-up. See Figure 8 for
clock mode 10 timing.
Initiate a scan by writing a command byte to the conver-
sion register. The MAX1221/MAX1223/MAX1343 then
power up, scan all requested channels, store the results
in the FIFO, and shut down. After the scan is complete,
EOC is pulled low and the results are available in the
FIFO. If a temperature measurement is requested, the
temperature result precedes all other FIFO results. EOC
stays low until CS is pulled low again. Wait until all con-
versions are complete before reading the FIFO. SPI
communications to the DAC and GPIO registers are per-
mitted during conversion. However, coupled noise may
result in degraded ADC SNR.
In clock mode 11, acquisitions and conversions are ini-
tiated by writing a command byte to the conversion
register and are performed one at a time using the
SCLK as the conversion clock. Scanning, averaging
and the FIFO are disabled, and the conversion result is
available at DOUT during the conversion. Output data
is updated on the rising edge of SCLK in clock mode
11. See Figure 9 for clock mode 11 timing.
Figure 9. Clock Mode 11—Externally Timed Acquisition, Sampling, and Conversion without CNVST
36
DOUT
SCLK
EOC
DIN
CS
______________________________________________________________________________________
Conversions Using the Serial Interface
Conversions Using the Serial Interface
Externally Clocked Acquisitions and
Internally Timed Acquisitions and
ADC Conversions in Clock Mode 11
ADC Conversions in Clock Mode 10
(ACQUISITION1)
(CONVERSION BYTE)
MSB1
(CONVERSION1)
Initiate a conversion by writing a command byte to the
conversion register followed by 16 SCLK cycles. If CS
is pulsed high between the eighth and ninth cycles, the
pulse width must be less than 100µs. To continuously
convert at 16 cycles per conversion, alternate 1 byte of
zeros (NOP byte) between each conversion byte. If 2
NOP bytes follow a conversion byte, the analog cells
power down at the end of the second NOP. Set the
FBGON bit to one in the reset register to keep the inter-
nal bias block powered.
If reference mode 00 is requested, or if an external refer-
ence is selected but a temperature measurement is being
requested, wait 45µs with CS high after writing the con-
version byte to extend the acquisition and allow the inter-
nal reference to power up. To perform a temperature
measurement, write 24 bytes (192 cycles) of zeros after
the conversion byte. The temperature result appears on
DOUT during the last 2 bytes of the 192 cycles.
The conversion time for each scan is based on a num-
ber of different factors: conversion time per sample,
samples per result, results per scan, if a temperature
measurement is requested, and if the external refer-
ence is in use. Use the following formula to calculate
the total conversion time for an internally timed conver-
sion in clock mode 00 and 10 (see the Electrical
Characteristics , as applicable):
where:
t
and reference mode selected.)
CNV
= t
t
CNV
DOV
x n
(where t
AVG
Total conversion time =
x n
LSB1
DOV
SCAN
(ACQUISITION2)
Conversion-Time Calculations
is dependent from the clock
+ t
TS
+ t
MSB2
INT-REF,SU