MAX1243BCSA Maxim Integrated Products, MAX1243BCSA Datasheet - Page 37

• Manufacturer Part Number: MAX1243BCSA
• Description: ADC (A/D Converters) Integrated Circuits (ICs)
• Manufacturer: Maxim Integrated Products

Specifications of MAX1243BCSA

• Number Of Adc Inputs: 1
• Architecture: SAR
• Conversion Rate: 73 KSPs
• Resolution: 10 bit
• Input Type: Voltage
• Interface Type: 3-Wire (SPI, QSPI, Microwire)
• Voltage Reference: External
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 2.7 V
• Maximum Power Dissipation: 471 mW
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: SO-8
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: No

n
n
to one unless [SCAN1, SCAN0] = 10
t
(58.1µs); set to zero if temperature measurement is not
requested
t
conversion using the external reference is requested
In clock mode 01, the total conversion time depends on
how long CNVST is held low or high. Conversion time in
externally clocked mode (CKSEL1, CKSEL0 = 11)
depends on the SCLK period and how long CS is held
high between each set of eight SCLK cycles. In clock
mode 01, the total conversion time does not include the
time required to turn on the internal reference.
Figures 10–13 detail the timing diagrams for writing to
the DAC and GPIOs. Figure 10 shows the timing speci-
Figure 10. DAC/GPIO Serial-Interface Timing (Clock Modes 00, 01, and 10)
TS
INT-REF,SU
AVG
SCAN
= time required for temperature measurement
= samples per result (amount of averaging)
= number of times each channel is scanned; set
SCLK
DOUT
DIN
CS
12-Bit, Multichannel ADCs/DACs with FIFO,
= t
t
CSPWH
WU
______________________________________________________________________________________
t
(external-reference wake-up); if a
DOE
t
t
CSS
DS
1
Temperature Sensing, and GPIO Ports
D15
t
DH
D15
2
D7
D14
t
DAC/GPIO Timing
CL
D14
D6
t
CH
3
D13
t
DOT
D13
D5
4
D12
fications for clock modes 00, 01, and 10. Figure 11
shows the timing specifications for clock mode 11.
Figure 12 details the timing specifications for the DAC
input select register and 2 bytes to follow. Output data
is updated on the rising edge of SCLK in clock mode
11. Figure 13 shows the GPIO timing. Figure 14 shows
the timing details of a hardware LDAC command DAC-
register update. For a software-command DAC-register
update, t
lows the last data bit in the software command word.
Drive LDAC low to transfer the content of the input reg-
isters to the DAC registers. Drive LDAC permanently
low to make the DAC register transparent. The DAC
output typically settles from zero to full scale within ±1
LSB after 2µs. See Figure 14.
D12
D4
5
D11
S
is valid from the rising edge of CS, which fol-
D1
D1
32
16
8
D0
t
CSH
D0
LDAC Functionality
t
DOD
37