FW82371EBSL37M Intel, FW82371EBSL37M Datasheet
FW82371EBSL37M
Specifications of FW82371EBSL37M
Related parts for FW82371EBSL37M
FW82371EBSL37M Summary of contents
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... Notice: The Intel 82371AB PIIX4, Intel may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are documented in this Specification Update. ® ® 82371EB PIIX4E, and Intel 82371MB PIIX4M Document Number: 297738-017 ...
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... Intel Corporation www.intel.com or call 1-800-548-4725 Intel, Pentium and Xeon and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States or other countries. *Other names and brands may be claimed as the property of others. Copyright © 1997–2002, Intel Corporation 2 ® ...
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... R Contents Revision History................................................................................................................... 4 Preface ................................................................................................................................ 5 Specification Changes....................................................................................................... 13 Errata................................................................................................................................. 22 Specification Clarifications ................................................................................................ 35 Documentation Changes................................................................................................... 52 Specification Update ® Intel 82371AB PIIX4, 82371EB PIIX4E, 82371MB PIIX4M 3 ...
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... Intel 82371AB PIIX4, 82371EB PIIX4E, 82371MB PIIX4M Revision History Rev. -001 Initial Release -002 Added PIIX4 Errata #11 -003 Added Specification Change #2, Errata #12 and #13, and Documentation Change #6 -004 Added Specification Change #3, Errata #14, Specification Clarifications #18 and #19, Documentation Changes #7 and #8 -005 Added Errata #15 and Specification Clarification #20 ...
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... Affected Documents/Related Documents ® Intel 82371AB PIIX4 datasheet Intel 82371AB (PIIX4) PCI ISA IDE Xcelerator Timing Specification Nomenclature Specification Changes are modifications to the current published specifications. These changes will be incorporated in the next release of the specifications. Errata are design defects or errors. Errata may cause the 82371AB PIIX4, 82371EB PIIX4E, and 82371MB PIIX4M, behavior to deviate from published specifications ...
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... Intel 82371AB PIIX4, 82371EB PIIX4E, 82371MB PIIX4M Component Identification via Programming Interface ® The Intel 82371AB PIIX4, 82371EB PIIX4E, and 82371MB PIIX4M may be identified by the following register contents: Stepping 82371AB PIIX4 A-0, A-1, B-0 82371EB PIIX4E A-0 82371MB PIIX4M A-0 NOTES: 1 ...
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... PIIX4E A-0 82371MB PIIX4M Stepping PIIX4M A-0 PIIX4M A-0 PIIX4M A-0 PIIX4M A-0 PIIX4M A-0 Specification Update ® Intel 82371AB PIIX4, 82371EB PIIX4E, 82371MB PIIX4M S-Spec Top Marking FW82371EB Q591ES FW82371EB Q592ES FW82371EB Q593ES FW82371EB Q594ES FW82371EB Q597ES FW82371EB Q598ES FW82371EB Q599ES ...
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... The following table indicates the Specification Changes, Errata, Specification Clarifications or Documentation Changes, which apply to the listed Intel 82371MB PIIX4M steppings. Intel intends to fix some of the errata in a future stepping of the component and to account for the other outstanding issues through documentation or Specification Changes as noted ...
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... DC Spec Change for all CPU CMOS I/F Signals to 9.7mA @ 450mV (PIIX4E and PIIX4M only) 20 USB Clock PPM 21 Removal of SERIRQ Low Pulse Specification 22 ISA Signal Behavior During Reset Specification Update ® Intel 82371AB PIIX4, 82371EB PIIX4E, 82371MB PIIX4M SPECIFICATION CHANGES for SMI# Changes 450 ...
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... Intel 82371AB PIIX4, 82371EB PIIX4E, 82371MB PIIX4M NO. PIIX4 Steppings Plans PIIX4E PIIX4M NoFix NoFix NoFix NoFix X Fix NoFix NoFix NoFix X Fix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix X X Fix NoFix NoFix NoFix ERRATA Burst Events May Cause LVL2 or LVL3 ...
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... Do Not Use 4-Clock Serial IRQ Start Frame Width When CLKRUN# Is Enabled 25 SLP# Connectivity in Multi-Processor Systems 26 Serial IRQ Enable Clarification 27 Interrupt Deassertion (only 0.35 µ process device) (PIIX4E and PIIX4M only) 28 PIORDY/SIORDY Minimum Deassertion Time Specification Update ® Intel 82371AB PIIX4, 82371EB PIIX4E, 82371MB PIIX4M SPECIFICATION CLARIFICATIONS 11 ...
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... Interval Timer for IRQ0 3 Bus Master Activity for Burst Events 4 IRQ9 and IRQ9OUT# Pin Locations 5 PIO0 Timing Values 6 Sleep and Deep Sleep for Intel 7 SMI# Minimum Deassertion Time 8 Datasheet t37 Correction 9 Corrections to Simplified Block Diagram, Table 55, and Figure 34 10 Table 50 STD Max Value ...
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... HI, not active level LO. The name of this pin is changed to IRQ9OUT/GPO29. This change applies to all steppings of the PIIX4/PIIX4E/PIIX4M and is planned to be incorporated into the next revisions of the PIIX4 datasheet and datasheet addendum. Specification Update ® Intel 82371AB PIIX4, 82371EB PIIX4E, 82371MB PIIX4M 3Dh 00h Read only ...
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... Intel 82371AB PIIX4, 82371EB PIIX4E, 82371MB PIIX4M 4. CLKRUN# Re-Assertion The PIIX4 datasheet on page 210, Section 11.2.3, PCI Clock Control, states if no other device in the system denies the request to stop before the fifth PCI clock, then the PIIX4 asserts the PCI_STP#. Any device must deny the request to stop before the fourth PCI clock. ...
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... A manufacturing ID field (0F8h) of PIIX4E functions 0–3 may return a value of 28h or 30h. This register is a RESERVED REGISTER and should not be accessed. This change applies to all steppings of the PIIX4E and is planned to be incorporated into the next revision of the PIIX4 datasheet. Specification Update ® Intel 82371AB PIIX4, 82371EB PIIX4E, 82371MB PIIX4M 15 ...
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... Intel 82371AB PIIX4, 82371EB PIIX4E, 82371MB PIIX4M 12 for SMI# Changes 450 The DC Characteristics for SMI#, as specified in the 82371AB (PIIX4) PCI ISA IDE Xcelerator Timing Specification datasheet addendum is changed from 400 mV to 10mA @ 450 mV to accommodate stronger external pull-up resistors. 7:0 ...
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... THT_EN set, the PIIX4E will enter the Stop Grant/Quick Start state without throttle. Upon a break event, the PIIX4E will re-enter the Stop Grant/Quick Start state with Throttle. Specification Update ® Intel 82371AB PIIX4, 82371EB PIIX4E, 82371MB PIIX4M Register Read CC_EN STP_CLK_EN ...
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... Intel 82371AB PIIX4, 82371EB PIIX4E, 82371MB PIIX4M 15. RI# and USB Generate an SCI (PIIX4E and PIIX4M only) The PIIX4E/PIIX4M do not have the ability to generate an SCI upon the setting of RI_STS or USB_STS. The PIIX4E/PIIX4M can generate an SCI upon the setting of RI_STS or USB_STS. The SCI_EN bit (PM base + 04h bit 0) and the RI_EN (PM + 0Eh bit 10) must be set to enable the SCI generation from RI assertion ...
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... Clock Frequency Tolerance being changed from 2500 PPM to 500 PPM. The footnote associated with this parameter will have the following sentence added: “PPM sources are external to this component.” Specification Update ® Intel 82371AB PIIX4, 82371EB PIIX4E, 82371MB PIIX4M Base + (20h) 00h Read/Write ...
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... Intel 82371AB PIIX4, 82371EB PIIX4E, 82371MB PIIX4M 21. Removal of SERIRQ Low Pulse Specification The PIIX4 Timing Specification incorrectly specifies t153 SERIRQ active low pulse of 100nS. This is not a required specification. The PIIX4/PIIX4E/PIIX4M will correctly sample SERIRQ as long as the setup time (t151) and hold time (t152) are met. The t153 specification will be removed from the next revision of the timing specification ...
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... R Specification Update ® Intel 82371AB PIIX4, 82371EB PIIX4E, 82371MB PIIX4M This page is intentionally left blank. 21 ...
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... Intel 82371AB PIIX4, 82371EB PIIX4E, 82371MB PIIX4M Errata Burst Events May Cause LVL2 or LVL3 Register Reads to Be Missed 1. Problem: Burst events that occur after Burst Enable bit (BST_EN) has been set and before the Processor Level 2 (LVL2) or Processor Level 3 (LVL3) register read may cause the LVL2 or LVL3 read to be missed ...
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... BIOS must ensure that the proper value is written into the GPO register prior to enabling the signal as a GPO. Status: This will not be fixed in PIIX4/PIIX4E/PIIX4M. This was incorporated into the PIIX4 datasheet as a change to the specification. Specification Update ® Intel 82371AB PIIX4, 82371EB PIIX4E, 82371MB PIIX4M Comments Value 0 No GPO[31] 1 ...
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... Status: This erratum will not be fixed in PIIX4/PIIX4E/PIIX4M. This erratum is planned to be incorporated into the next revision of the PIIX4 datasheet as a specification change. Intel is working with Microsoft to incorporate the workaround into their UHCI driver. Microsoft will make this workaround available in the Beta 1 release of Memphis. Microsoft will provide a fix to the OSR2 ...
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... PCNTRL register are supported. Upon assertion of the THRM# signal, no special provisions need to be taken. The PIIX4E and PIIX4M will guarantee that STPCLK# signal stays high for at least 32 s (26.7 s for PIIX4M). Specification Update ® Intel 82371AB PIIX4, 82371EB PIIX4E, 82371MB PIIX4M Bandwidth Reclam ation Loop Pseudo QH ...
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... Intel 82371AB PIIX4, 82371EB PIIX4E, 82371MB PIIX4M Device Trap 6. Problem: When the PIIX4/PIIX4E/PIIX4M Device Trap logic is enabled for Devices 0-13, they forward the I/O access cycles for the device to the EIO/ISA and IDE Bus. Implication: Accesses to devices in a powered down state could cause unpredictable results. ...
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... Start/Stop Bus Master bit, and retry the transfer. Note that this errata does not occur using PIO mode or Ultra DMA/33 mode. Status: This will not be fixed on PIIX4/PIIX4E/PIIX4M. This is planned to be incorporated into the PIIX4 datasheet as a change to the specification. Specification Update ® Intel 82371AB PIIX4, 82371EB PIIX4E, 82371MB PIIX4M 27 ...
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... Intel 82371AB PIIX4, 82371EB PIIX4E, 82371MB PIIX4M USB-PCI Latency 11. Problem: Under certain circumstances, PIIX4/PIIX4E/PIIX4M will start an isochronous USB transfer when there is not enough time to successfully complete the transaction. Implication: This failure only occurs when some PCI devices introduce large (>15 µs) latencies on the PCI bus in combination with the USB transfer ...
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... IOAPIC and will not work correctly. Workaround: Program the appropriate input of the IOAPIC to active level HI. Status: This will not be fixed in the PIIX4/PIIX4E/PIIX4M. This is planned to be incorporated into the PIIX4 datasheet as a specification change. Specification Update ® Intel 82371AB PIIX4, 82371EB PIIX4E, 82371MB PIIX4M 29 ...
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... PIIX4/PIIX4E/PIIX4M I/O trap SMI includes device traps and APM register write traps (0B2h). Implication: The errata condition can occur in Intel Pentium II processor/PIIX4x systems that use I/O Trap SMI with STPCLK# throttling enabled. The observed effect of the erratum is a system hang, although it may also result in indeterminate code behavior that could cause data corruption ...
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... This will not be fixed in the PIIX4/PIIX4E/PIIX4M. This is planned to be incorporated into the PIIX4 datasheet as a change to the specification. This should be corrected for in ACPI aware operating systems. Contact your Operating System vendor for schedule and release information. Specification Update ® Intel 82371AB PIIX4, 82371EB PIIX4E, 82371MB PIIX4M 31 ...
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... Intel 82371AB PIIX4, 82371EB PIIX4E, 82371MB PIIX4M USB Dribble 19. Problem: A USB receive packet with a bitstuff following then transmission of CRC, coupled with a dribble bit due to prop delays through cables and HUBs may be incorrectly interpreted by the USB host controller state machine as a poorly formed EOP. ...
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... USB device is functional (after the resume), to the USB device no longer works (after the resume) – in which case a system reboot must be done to obtain functionality of that USB device. In all cases the rest of the system does resume. Specification Update ® Intel 82371AB PIIX4, 82371EB PIIX4E, 82371MB PIIX4M 33 ...
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... Intel 82371AB PIIX4, 82371EB PIIX4E, 82371MB PIIX4M Workaround: None. Status: This will not be fixed in the PIIX4, PIIX4E, PIIX4M Specification Update ...
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... Section 2.1.12, Other System and Test Signals, of the PIIX4 datasheet defines the CONFIG [1] signal. In addition to controlling the polarity of INIT and CPURST, this signal also controls the latching of NMI, SMI#, INTR, and INIT Intel Pentium Processor-based system (CONFIG[1]=0) NMI, SMI#, INTR, and INIT flow unlatched to the processor in all power managed states ...
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... Intel 82371AB PIIX4, 82371EB PIIX4E, 82371MB PIIX4M IRQ8# Routing 3. The RTC interrupt is connected to ISA IRQ8#, and is internally routed within the PIIX4/PIIX4E/PIIX4M. If the internal RTC is enabled (bit 0 of the RTCCFG is set ) , the PIIX4/PIIX4E/PIIX4M’s IRQ8# pin should be programmed as a general-purpose input, GPI[6] (by setting bit 14 of the PIIX4/PIIX4E/PIIX4M’ ...
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... PIIX4 datasheet. SCI Interrupt Interrupt KEY IRQ9 not used by that function 1 = IRQ9 used by that function non-shared = IRQ9 not shared internally between functions shared = IRQ9 shared internally between functions Specification Update ® Intel 82371AB PIIX4, 82371EB PIIX4E, 82371MB PIIX4M SMBus PIRQ ISA IRQ9 ...
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... Intel 82371AB PIIX4, 82371EB PIIX4E, 82371MB PIIX4M SERIRQ Sampling Phase 5. When referring to the state of the SERIRQ signal the verbiage in section 8.7.1 of the datasheet uses the words active and low interchangeably as well as the words inactive and high. This text has been changed to only use the words low and high when referring to the state of the SERIRQ signal. The PIIX4’ ...
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... In addition, writes generate an SMI, if the APMC_EN bit (PCI function 3, offset 58h, bit 25) and the IOSE bit (PCI function 3, offset 04h, bit 0) are set to 1. Reads do not generate an SMI. Specification Update ® Intel 82371AB PIIX4, 82371EB PIIX4E, 82371MB PIIX4M Sequencing Circuit REF 0B2h ...
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... Intel 82371AB PIIX4, 82371EB PIIX4E, 82371MB PIIX4M 7.1.3 PCICMD—PCI COMMAND REGISTER (FUNCTION 3) Address Offset: Default Value: Attribute: This register controls access to the I/O space registers. Bit 0 I/O Space Enable (IOSE). 1=Enable. 0=Disable. This bit controls the access to the SMBus I/O space registers whose base address is described in the SMBus Base Address register ...
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... PIIX4 will transition to the soft off state and immediately resume. If PWROK is deasserted, the Power Button Override logic will not function. This bit is only set by hardware and can only be reset by writing a one to this bit position. Specification Update ® Intel 82371AB PIIX4, 82371EB PIIX4E, 82371MB PIIX4M Base + (00h) 00h Read/Write ...
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... Intel 82371AB PIIX4, 82371EB PIIX4E, 82371MB PIIX4M RTC Status Bit Clarification 10. Section 7.2.1 of the PIIX4 datasheet defines the RTC status bit. The RTC_EN bit in the PMEN register (base + 02h, bit 10) gates the setting of the RTC_STS bit. RTC_EN must be set in order to set the RTC_STS bit upon an RTC alarm ...
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... For the case where a 64-Kbyte DT is required, then it must be aligned on a 64-Kbyte boundary. This clarification applies to all steppings of the PIIX4/PIIX4E/PIIX4M and is planned to be incorporated into the next revision of the PIIX4 datasheet. Specification Update ® Intel 82371AB PIIX4, 82371EB PIIX4E, 82371MB PIIX4M 43 ...
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... Intel 82371AB PIIX4, 82371EB PIIX4E, 82371MB PIIX4M RTC Index Register Read 17. The PIIX4 datasheet, Section 6.1.14, MISCSUP—Miscellaneous Support Register (Function 2), does not clearly document the steps for reading the RTC Index Register. The following algorithm should be followed before reading the RTC Index Register: 1 ...
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... None of the other registers should be accessed if this bit is set. Note that there may be moderate latency before the transaction begins and the Host Busy bit gets set. Specification Update ® Intel 82371AB PIIX4, 82371EB PIIX4E, 82371MB PIIX4M Base + (00h) 00h Read/Write ...
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... Intel 82371AB PIIX4, 82371EB PIIX4E, 82371MB PIIX4M In the PIIX4 datasheet, Page 150, Section 7.3.3, SMBHSTCNT - SMBUS HOST CONTROL REGISTER (IO), Bit 0 should be changed to read: 7.3.3 SMBHSTCNT—SMBUS HOST CONTROL REGISTER (IO) I/O Address: Default Value: Attribute: The control register is used to enable SMBus controller host interface functions. Reads to this register clears the host interface’ ...
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... I/O read cycles targeting the XBUS or enabled Generic Decode Chip Selects.” This clarification applies to all steppings of the PIIX4/PIIX4E/PIIX4M and is planned to be incorporated into the next revision of the PIIX4 datasheet. Specification Update ® Intel 82371AB PIIX4, 82371EB PIIX4E, 82371MB PIIX4M 47 ...
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... Intel 82371AB PIIX4, 82371EB PIIX4E, 82371MB PIIX4M Correction to the USB Bandwidth Reclamation Erratum Workaround 23. The workaround for the USB Bandwidth Reclamation Erratum workaround is not correctly documented in Errata number 4. The following changes are required. 1) The Queue Head Link Pointer must be set to point to the next Queue Head, not the Pseudo TD as indicated ...
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... PIIX4E/PIIX4M interrupt output goes directly to the processor intermediary circuitry which may also miss the short deassertion pulse described below. Consult the Microprocessor Specification v1.4 available on developer.intel.com for details on these operating modes. A high priority interrupt occuring just as the PIIX4E/PIIX4M receives INTACK for a preceding low priority interrupt can cause a small interrupt deassertion time from the new PIIX4E/PIIX4M (both 0 ...
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... Intel 82371AB PIIX4, 82371EB PIIX4E, 82371MB PIIX4M PIORDY/SIORDY Minimum Deassertion Time 28. PIORDY and SIORDY are active high inputs to the PIIX4/PIIX4E/PIIX4M. When PIORDY/SIORDY is high the IDE cycle completes without any additional wait states. An IDE device can drive PIORDY/SIORDY low to indicate that wait states are required to complete the cycle ...
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... R Specification Update ® Intel 82371AB PIIX4, 82371EB PIIX4E, 82371MB PIIX4M This page is intentionally left blank. 51 ...
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... Intel 82371AB PIIX4, 82371EB PIIX4E, 82371MB PIIX4M Documentation Changes PCI Revision ID (RID) Register Values 1. Change: The RID register (PCI offset 08h) values for functions 0,1, 2, and 3 are shown below: 82371AB PIIX4, 82371EB PIIX4E, and 82371MB PIIX4M Function Not updated in datasheet. This is the standard reference document. ...
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... The PIIX4 datasheet, section 11.2.1, Host Clock Control Mechanisms, identifies Stop Clock State and Deep Sleep State as being available for Intel Pentium II processors only, which is incorrect. The Sleep State and the Deep Sleep State are for Pentium II processors only, the Stop Clock State is available for all processor types ...
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... Intel 82371AB PIIX4, 82371EB PIIX4E, 82371MB PIIX4M Corrections to Simplified Block Diagram, Table 55, and Figure 34 9. The PIIX4 datasheet, Simplified Block Diagram, on page 3, the PIIX4 Pinout on page 270, and Table 55 PIXX4 Alphabetical Pin List, starting on page 271, have several typographical errors. ...
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... The PIIX4 datasheet, Section 2.1.6, CPU Interface Signals, on page 26, describes INIT as remaining asserted for approximately 64 PCI clocks before being negated. This amount is actually 16 PCI clocks, which is consistent with other discussion on this signal. Specification Update ® Intel 82371AB PIIX4, 82371EB PIIX4E, 82371MB PIIX4M 55 ...