FW82371EBSL37M Intel, FW82371EBSL37M Datasheet - Page 44

• Manufacturer Part Number: FW82371EBSL37M
• Description: Embedded Processor 352-Pin BGA
• Manufacturer: Intel

Specifications of FW82371EBSL37M

• Package: 352BGA

Intel
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82371AB PIIX4, 82371EB PIIX4E, 82371MB PIIX4M
RTC Index Register Read
The PIIX4 datasheet, Section 6.1.14, MISCSUP—Miscellaneous Support Register (Function 2),
does not clearly document the steps for reading the RTC Index Register. The following algorithm
should be followed before reading the RTC Index Register:
This clarification applies to all steppings of the PIIX4/PIIX4E/PIIX4M and is planned to be
incorporated into the next revision of the PIIX4 datasheet.
GPI[1] Minimum Assertion
The PIIX4 datasheet, Section 7.2.5, GPSTS—General Purpose Status Register, does not clearly
document the required behavior for GPI_STS. The following description will be added to the
description for GPSTS[9] (GPI_STS). GPI[1]# must be asserted for a minimum of 2 PCI Clocks
during runtime, or 2 RTC Clocks during suspend for GPI_STS to be set.
This clarification applies to all steppings of the PIIX4/PIIX4E/PIIX4M and is planned to be
incorporated into the next revision of the PIIX4 datasheet.
RSMRST# Behavior
The PIIX4 datasheet, Section 2.1.10, Power Management Signals, identifies the signal description
of the Power Management Signals. The following should be added to the description of
RSMRST#.
It will reset the SM Bus Host and Slave controllers in the suspend well and will assert SUS[A:C]#.
The assertion of SUS[A-C]# will generally initiate the deassertion of PWROK. RSMRST#
assertion will then generally reset the entire system.
This clarification applies to all steppings of the PIIX4/PIIX4E/PIIX4M and is planned to be
incorporated into the next revision of the PIIX4 datasheet.
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Disable Alternate Access mode (function 0, B0h, bit 5)
Set the RTC Index Read Enable bit (RTCIREN)
Read the RTC Index register (70h) (bits [6:0] provide RTC Index value, bit 7 is
indeterminate)
Disable the RTC Index Read Enable bit
Enable Alternate Access mode
Read the RTC Index register (bit 7 is the NMI enable bit, bits [6:0] are indeterminate)
Disable Alternate Access mode (function 0, B0h, bit 5)
Specification Update
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