FW82371EBSL37M Intel, FW82371EBSL37M Datasheet - Page 42

• Manufacturer Part Number: FW82371EBSL37M
• Description: Embedded Processor 352-Pin BGA
• Manufacturer: Intel

Specifications of FW82371EBSL37M

• Package: 352BGA

Intel
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82371AB PIIX4, 82371EB PIIX4E, 82371MB PIIX4M
RTC Status Bit Clarification
Section 7.2.1 of the PIIX4 datasheet defines the RTC status bit. The RTC_EN bit in the PMEN
register (base + 02h, bit 10) gates the setting of the RTC_STS bit. RTC_EN must be set in order to
set the RTC_STS bit upon an RTC alarm.
This clarification applies to all steppings of the PIIX4/PIIX4E/PIIX4M and is planned to be
incorporated into the next revision of the PIIX4 datasheet.
7.2.1
I/O Address:
Default Value:
Attribute:
SCI_EN Bit Clarification
Section 7.2.3, PMCNTRL Power Management Control Register (IO), of the PIIX4 datasheet,
defines the SCI enable bit. The SCI_EN bit in the PMCNTRL register enables the generation of
SCI from 4 sources; PWRBTN#, LID, THRM#, and GPI1#. If this bit is enabled and the individual
enable bits from these sources are set (PWRBTN_EN, LID_EN, THRM_EN, and GPI_EN), an
SCI is generated. If this bit is disabled and the individual enable bits from these sources are set, an
SMI# is generated. Note that there are two sources of SCI (BIOS_RLS, TMROF_STS) that are not
controlled by this register. To disable SCI from these sources, their respective enable bits
(GBL_EN, TMROF_EN) must be disabled.
This clarification applies to all steppings of the PIIX4/PIIX4E/PIIX4M and is planned to be
incorporated into the next revision of the PIIX4 datasheet.
7.2.3
I/O Address:
Default Value:
Attribute:
Thermal Override Initiates Throttling Even in Clock Control State
If THRM# is asserted for more than 2 seconds while the PIIX4 is in a Stop Grant state, the PIIX4
will still initiate STPCLK# throttling. Once THRM# is deasserted the PIIX4 will return to the
clock control state.
This clarification applies to all steppings of the PIIX4/PIIX4E/PIIX4M and is planned to be
incorporated into the next revision of the PIIX4 datasheet.
10
Bit
Bit
0
PMSTS POWER MANAGEMENT STATUS REGISTER (IO)
PMCNTRL POWER MANAGEMENT CONTROL REGISTER (IO)
RTC Status (RTC_STS)—R/WC. 1=RTC alarm has been signaled. 0=RTC alarm has not been
signaled. This bit is set when the internal RTC asserts its IRQ8 signal and the RTC_EN bit is set.
This bit is only set by hardware and can only be reset by writing a one to this bit position.
LID_STS, THRM_STS, or GPI_STS bits. 0=Disable. Note that this register does not disable SCI
generation from the Power Management Timer or BIOS Release bit.
SCI Enable(SCI_EN)—R/W. 1=Enable generation of SCI upon setting of PWRBTN_STS,
Base + (00h)
00h
Read/Write
Base + (04h)
0000h
Read/Write
Description
Description
Specification Update
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