FW82371EBSL37M Intel, FW82371EBSL37M Datasheet - Page 49

• Manufacturer Part Number: FW82371EBSL37M
• Description: Embedded Processor 352-Pin BGA
• Manufacturer: Intel

Specifications of FW82371EBSL37M

• Package: 352BGA

26.
27.
Specification Update
R
Serial IRQ Enable Clarification
Section 4.1.11, SERIRQC-Serial IRQ Control Register (Function 0) of the PIIX4 datasheet, Bit-7
(Serial IRQ Enable) must be set only after the SERIRQ/GPI7 Signal Pin Select (Function 0
GENCFG) has been set.
Interrupt Deassertion (only 0.35u process device) (PIIX4E and PIIX4M only)
The PIIX4E/PIIX4M has transitioned to a smaller and faster manufacturing process
(0.35u process). The result of this transition is largely transparent for the majority of operations;
however, an exception has been identified for some operating systems, most notably OS/2.
This issue is seen when a system is configured in Virtual Wire mode where 8259 generated
interrupts are delivered through the IO APIC which is configured for edge triggered interrupts on
its inputs. This issue could also manifest itself in other modes such as PIC mode or uni-processor
mode where the PIIX4E/PIIX4M interrupt output goes directly to the processor, or to intermediary
circuitry which may also miss the short deassertion pulse described below. Consult the
Microprocessor Specification v1.4 available on developer.intel.com for details on these operating
modes.
A high priority interrupt occuring just as the PIIX4E/PIIX4M receives INTACK for a preceding
low priority interrupt can cause a small interrupt deassertion time from the new PIIX4E/PIIX4M
(both 0.35u) which can be missed at either the IO APIC or the processor, depending on
configuration, and likely cause a system hang. The interrupt deassertion time as specified for the
original 8259 interrupt controller is a variable value, and the PIIX4E/PIIX4M was designed to
meet this specification and does. However, on the old PIIX4E (0.6u), the interrupt deassertion time
was on the order of 100 ns, where on the new PIIX4E/PIIX4M this time can be as short as 3 ns for
the above described condition. While this still meets the original 8259 interrupt controller
specification, it does not meet the interrupt input minimum deassertion time requirements for the
IO APIC or the Intel Pentium II, Intel
Pentium
LINT[1:0] inputs at the processor are also configuration pins at reset, the interrupt signal is often
routed through configuration circuitry first, and then to the processor. On some system designs, it
has also been identified that the short deassertion pulse never makes it through this circuitry; this
may also require detection of the short deassertion edge, and subsequent pulse stretching circuitry
to meet minimum deassertion time for the processor.
To address the Virtual Wire Mode through the IO APIC problem, configure Virtual Wire mode to
operate through the processor’s local APIC, vs. the IO APIC, and also for level triggered mode via
EXTInt (default).
A workaround for OS/2 has been identified for the anomaly. The OS/2 driver uses an environment
variable switch to force the change to the correct virtual wire mode. The variable in config.sys is:
If this problem is experienced in uni-processor or PIC mode, circuitry to catch the short deassertion
pulse from the PIIX4E/PIIX4M and stretch it to greater than 2 BCLKs for input to the processor
can be employed.
Locate PSD=OS2APIC.PSD statement and add “ /PREC=LID” to the end of it.
Your config.sys PSD statement should read as follows: PSD=OS2APIC.PSD /PREC=LID
®
III Xeon™ processors (refer to respective datasheets for these specifications). As the
Intel
®
Pentium
®
82371AB PIIX4, 82371EB PIIX4E, 82371MB PIIX4M
®
III, Intel
®
Pentium
®
II Xeon™, and Intel
®
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