FW82371EBSL37M Intel, FW82371EBSL37M Datasheet - Page 39

• Manufacturer Part Number: FW82371EBSL37M
• Description: Embedded Processor 352-Pin BGA
• Manufacturer: Intel

Specifications of FW82371EBSL37M

• Package: 352BGA

6.
7.
8.
Specification Update
R
RI# Pulse Width Requirement
Section 11.4.2 of the PIIX4 datasheet specifies a 2 RTC pulse width requirement for GPI1,
IRQ[15:9,7:3,1], and USB resume events. This list should also include RI#.
This clarification applies to all steppings of the PIIX4/PIIX4E/PIIX4M and is planned to be
incorporated into the next revision of the PIIX4 datasheet.
“The GPI1, EXTSMI#, IRQ[15:9,7:3,1], and USB resume events must be active for a minimum of
64 s (approximately 2 TC clock periods) for the resume to be recognized.”
Diode Requirement for V
Figure 2, in Section 2.3, of the PIIX4 datasheet provides an example V
Included in this circuit is a diode. The datasheet does not explicitly state that this diode should be a
Schottky diode.
This clarification applies to all steppings of the PIIX4/PIIX4E/PIIX4M and is planned to be
incorporated into the next revision of the PIIX4 datasheet.
SMI# Generation from APMC Write
To generate an SMI# by reading from the APMC Register it is necessary to enable both the
APMC_EN bit as well as the IOSE bit. The datasheet Sections 4.2.6.1 (APMC—Advanced Power
Management Control Port (IO)), 7.1.3 (PCICMD—PCI Command Register (Function 3)), and
7.1.16 (DEVACTB Device Activity B (Function 3)) do not state that it is necessary to set the
IOSE bit.
This clarification applies to all steppings of the PIIX4/PIIX4E/PIIX4M and is planned to be
incorporated into the next revision of the PIIX4 datasheet.
4.2.6.1
I/O Address:
Default Value:
Attribute: Read/Write
This register passes data (APM Commands) between the OS and the SMI handler. In addition,
writes can generate an SMI. PIIX4 operation is not effected by the data in this register.
Bit
7:0
APMC—ADVANCED POWER MANAGEMENT CONTROL PORT (IO)
APM Control Port (APMC). Writes to this register store data in the APMC Register and reads
return the last data written. In addition, writes generate an SMI, if the APMC_EN bit (PCI function
3, offset 58h, bit 25) and the IOSE bit (PCI function 3, offset 04h, bit 0) are set to 1. Reads do not
generate an SMI.
0B2h
00h
REF
Intel
Sequencing Circuit
®
82371AB PIIX4, 82371EB PIIX4E, 82371MB PIIX4M
Description
REF
Sequencing Circuit.
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