FW82371EBSL37M Intel, FW82371EBSL37M Datasheet - Page 27

• Manufacturer Part Number: FW82371EBSL37M
• Description: Embedded Processor 352-Pin BGA
• Manufacturer: Intel

Specifications of FW82371EBSL37M

• Package: 352BGA

9.
Problem:
Workaround: None.
Status:
10.
Problem:
Implication: In Bus Master IDE (BMIDE) mode, the PCI interface is prefetching data. If this prefetched data
Workaround: If the controller locks up, the BMIDE driver must timeout, reset the PIIX4/PIIX4E/PIIX4M
Status:
Specification Update
R
PCI Arbiter Advances when PC/PCI ISA Master Gets Retried by the Host
Controller
When a PC/PCI ISA master cycle gets retried (delayed transaction) by the host controller, the
PIIX4/PIIX4E/PIIX4M PCI Arbiter advances to a pending PCI master (USB or IDE). Affects
440BX-PIIX4x-MoonISA Docking platforms.
The 82443BX host controller will delay transaction (retry) a PC/PCI ISA master cycle
(PIIX4/PIIX4E/PIIX4M DMA controller in cascade mode) from PCI to DRAM. When the
PIIX4/PIIX4E/PIIX4M detect the retry, it will do a passive release on the PHLD# signal and allow
another PCI master (82443BX Arbiter) to acquire the bus. Following the passive release, the
PIIX4/PIIX4E/PIIX4M will un-intentionally advance the PCI arbiter to a pending PCI master
request (USB or IDE). The 82443BX expects to the next cycle from PIIX4/PIIX4E/PIIX4M to be
the delayed transaction cycle and will retry any other cycle (USB or IDE). The
PIIX4/PIIX4E/PIIX4M arbiter will stay on the USB or IDE bus master device until the delay
transaction timeout in the 82443BX. After the timeout the 82443BX drops the data possibly
resulting in a system hang.
This will not be fixed on PIIX4. This is planned to be incorporated into the PIIX4 datasheet as a
change to the specification. This erratum was fixed on PIIX4E and PIIX4M.
Bus Master IDE Timeout
During an IDE DMA write, the PIIX4/PIIX4E/PIIX4M IDE controller will invalidate the FIFO if
the IDE device deasserts its DREQ signal for greater than 1us. During the FIFO invalidation, the
PIIX4/PIIX4E/PIIX4M do not prevent a FIFO fill from PCI.
gets inserted into the IDE FIFO (during a FIFO invalidation due to DREQ deassertion > 1 µs) the
IDE controller will lock up. Any future reassertion of the DREQ signal will not be acknowledged
by the PIIX4/PIIX4E/PIIX4M IDE controller. BMIDE transactions will not complete on either the
primary or secondary channel.
Start/Stop Bus Master bit, and retry the transfer. Note that this errata does not occur using PIO
mode or Ultra DMA/33 mode.
This will not be fixed on PIIX4/PIIX4E/PIIX4M. This is planned to be incorporated into the PIIX4
datasheet as a change to the specification.
Intel
®
82371AB PIIX4, 82371EB PIIX4E, 82371MB PIIX4M
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