FW82371EBSL37M Intel, FW82371EBSL37M Datasheet - Page 52
FW82371EBSL37M
Manufacturer Part Number
FW82371EBSL37M
Description
Embedded Processor 352-Pin BGA
Manufacturer
Intel
Datasheet
1.FW82371EBSL37M.pdf
(55 pages)
Specifications of FW82371EBSL37M
Package
352BGA
- Current page: 52 of 55
- Download datasheet (322Kb)
Intel
Documentation Changes
1.
2.
3.
4.
52
®
82371AB PIIX4, 82371EB PIIX4E, 82371MB PIIX4M
PCI Revision ID (RID) Register Values
Change: The RID register (PCI offset 08h) values for functions 0,1, 2, and 3 are shown below:
82371AB PIIX4, 82371EB PIIX4E, and 82371MB PIIX4M
Not updated in datasheet. This is the standard reference document.
Interval Timer for IRQ0
Section 8.6 (Interrupt Controller) and Figure 5 (Interrupt Controller Block Diagram) in the
datasheet, incorrectly refer to Interval Timer 1 as the timer used by IRQ0 for the system timer
interrupt. IRQ0 is actually tied to Interval Timer 0.
PCI Bus Master Activity for Burst Events
Section 11.2.1, Host Clock Control Mechanisms, in the datasheet, incorrectly lists PCI Bus Master
Activity [BRLD_EN_BM] as a fast burst event. The BRLD_EN_BM bit is not supported.
IRQ9 and IRQ9OUT# Pin Locations
Table 55 (Alphabetical Pin List) and Figure 34 (PIIX4 Pinout) incorrectly document the pin
locations for IRQ9 and IRQ9OUT/GPO29. Pin F3 should be documented as IRQ9OUT#/GPO29
and pin U1 should be documented as IRQ9.
Function
0
1
2
3
PIIX4 A-0
00h
00h
00h
00h
PIIX4 A-1
00h
00h
00h
00h
PIIX4 B-0
Stepping
01h
01h
01h
01h
PIIX4E A-0
02h
01h
01h
02h
Specification Update
PIIX4M A-0
02h
01h
01h
03h
R
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