LFE2-50E-5F484I Lattice, LFE2-50E-5F484I Datasheet - Page 101
![no-image](/images/manufacturer_photos/0/3/380/lattice_sml.jpg)
LFE2-50E-5F484I
Manufacturer Part Number
LFE2-50E-5F484I
Description
FPGA 48000 CELLS 90NM (CMOS) 1.2
Manufacturer
Lattice
Series
ECP2r
Datasheet
1.LFE2-12E-5FN256C.pdf
(385 pages)
Specifications of LFE2-50E-5F484I
Number Of Logic Elements/cells
48000
Number Of Labs/clbs
6000
Total Ram Bits
396288
Number Of I /o
339
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-BBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q3220905AABC
- Current page: 101 of 385
- Download datasheet (3Mb)
Signal Descriptions
April 2008
© 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
General Purpose
P[Edge] [Row/Column Number*]_[A/B]
GSRN
NC
GND
V
V
V
V
V
XRES
PLLCAP
PLL, DLL and Clock Functions (Used as user programmable I/O pins when not in use for PLL or clock pins)
[LOC][num]_V
[LOC][num]_GPLL[T, C]_IN_A
[LOC][num]_GPLL[T, C]_FB_A
[LOC][num]_SPLL[T, C]_IN_A
[LOC][num]_SPLL[T, C]_FB_A
[LOC][num]_DLL[T, C]_IN_A
[LOC][num]_DLL[T, C]_FB_A
PCLK[T, C]_[n:0]_[3:0]
CC
CCAUX
CCIOx
CCPLL
REF1_x
4
, V
4
REF2_x
Signal Name
CCPLL
I/O
I/O
—
—
—
—
—
—
—
—
—
—
I
I
I
I
I
I
I
I
LatticeECP2/M Family Data Sheet
[Edge] indicates the edge of the device on which the pad is located. Valid
edge designations are L (Left), B (Bottom), R (Right), T (Top).
[Row/Column Number] indicates the PFU row or the column of the device on
which the PIC exists. When Edge is T (Top) or B (Bottom), only need to spec-
ify Row Number. When Edge is L (Left) or R (Right), only need to specify Col-
umn Number.
[A/B] indicates the PIO within the PIC to which the pad is connected. Some of
these user-programmable pins are shared with special function pins. These
pins, when not used as special purpose pins, can be programmed as I/Os for
user logic. During configuration the user-programmable I/Os are tri-stated
with an internal pull-up resistor enabled. If any pin is not used (or not bonded
to a package pin), it is also tri-stated with an internal pull-up resistor enabled
after configuration.
Global RESET signal (active low). Any I/O pin can be GSRN.
No connect.
Ground. Dedicated pins.
Power supply pins for core logic. Dedicated pins.
Auxiliary power supply pin. This dedicated pin powers all the differential and
referenced input buffers.
Dedicated power supply pins for I/O bank x.
PLL supply pins. Should be tied to V
unused.
Reference supply pins for I/O bank x. Pre-determined pins in each bank are
assigned as V
10K ohm +/-1% resistor must be connected between this pad and ground.
External capacitor connection for PLL.
Power supply pin for PLL: ULM, LLM, URM, LRM, num = row from center.
General Purpose PLL (GPLL) input pads: ULM, LLM, URM, LRM, num = row
from center, T = true and C = complement, index A,B,C...at each side.
Optional feedback GPLL input pads: ULM, LLM, URM, LRM, num = row from
center, T = true and C = complement, index A,B,C...at each side.
Secondary PLL (SPLL) input pads: ULM, LLM, URM, LRM, num = row from
center, T = true and C = complement, index A,B,C...at each side.
Optional feedback (SPLL) input pads: ULM, LLM, URM, LRM, num = row
from center, T = true and C = complement, index A,B,C...at each side.
DLL input pads: ULM, LLM, URM, LRM, num = row from center, T = true and
C = complement, index A,B,C...at each side.
Optional feedback (DLL) input pads: ULM, LLM, URM, LRM, num = row from
center, T = true and C = complement, index A,B,C...at each side.
Primary Clock pads, T = true and C = complement, n per side, indexed by
bank and 0,1,2,3 within bank.
4-1
REF
inputs. When not used, they may be used as I/O pins.
Description
Pinout Information
CC
even when the corresponding PLL is
DS1006
Pinout Information_01.8
Data Sheet DS1006
Related parts for LFE2-50E-5F484I
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
![LFE2-50E-5FN484C](/images/manufacturer_photos/0/3/381/lattice_semiconductor_tmb.jpg)
Part Number:
Description:
IC, LATTICEECP2 FPGA, 420MHZ, FPBGA-484
Manufacturer:
LATTICE SEMICONDUCTOR
Datasheet:
![LFE2-50E-H-EVN](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
Development Software Evaluation Board
Manufacturer:
Lattice
![LFE2-50E-VID-EV](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
Development Software LatticeECP2 Video Dev Kit
Manufacturer:
Lattice
Datasheet:
![LFE2-50E-D-EVN](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
MCU, MPU & DSP Development Tools LatticeMico32/DSP DEV BD/LatticeECP2
Manufacturer:
Lattice
Datasheet:
![LFE2-50E-H-EV](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
MCU, MPU & DSP Development Tools LatticeECP2 Eval Brd - Advanced
Manufacturer:
Lattice
Datasheet:
![LFE2-50E-L-EV](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
MCU, MPU & DSP Development Tools ECP-2 Standard Eval Board
Manufacturer:
Lattice
Datasheet:
![LFE2-50E-D-EV](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
MCU, MPU & DSP Development Tools LS Mico32/DSP Dev Br Brd for LS ECP2
Manufacturer:
Lattice
Datasheet:
![LFE2-50E-5F672C](/images/manufacturer_photos/0/3/381/lattice_semiconductor_tmb.jpg)
Part Number:
Description:
FPGA LatticeECP2 Family 48000 Cells 90nm (CMOS) Technology 1.2V 672-Pin FBGA
Manufacturer:
LATTICE SEMICONDUCTOR
Datasheet:
![LFE2-50E-5FN484I](/images/manufacturer_photos/0/3/381/lattice_semiconductor_tmb.jpg)
Part Number:
Description:
FPGA LatticeECP2 Family 48000 Cells 90nm (CMOS) Technology 1.2V 484-Pin FBGA
Manufacturer:
LATTICE SEMICONDUCTOR
Datasheet:
![LFE2-50E-5FN672C](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
IC FPGA 50KLUTS 500I/O 672-BGA
Manufacturer:
Lattice
Datasheet:
![LFE2-50E-6F484C](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
IC FPGA 50KLUTS 339I/O 484-BGA
Manufacturer:
Lattice
Datasheet:
![LFE2-50E-6FN484C](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
IC FPGA 50KLUTS 339I/O 484-BGA
Manufacturer:
Lattice
Datasheet:
![LFE2-50E-7FN484C](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
IC FPGA 50KLUTS 339I/O 484-BGA
Manufacturer:
Lattice
Datasheet:
![LFE2-50E-7FN672C](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
IC FPGA 50KLUTS 500I/O 672-BGA
Manufacturer:
Lattice
Datasheet:
![LFE2-50E-6FN672C](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
IC FPGA 48KLUTS 672FPBGA
Manufacturer:
Lattice
Datasheet: