LFE2-50E-5F484I Lattice, LFE2-50E-5F484I Datasheet - Page 88
![no-image](/images/manufacturer_photos/0/3/380/lattice_sml.jpg)
LFE2-50E-5F484I
Manufacturer Part Number
LFE2-50E-5F484I
Description
FPGA 48000 CELLS 90NM (CMOS) 1.2
Manufacturer
Lattice
Series
ECP2r
Datasheet
1.LFE2-12E-5FN256C.pdf
(385 pages)
Specifications of LFE2-50E-5F484I
Number Of Logic Elements/cells
48000
Number Of Labs/clbs
6000
Total Ram Bits
396288
Number Of I /o
339
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-BBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q3220905AABC
- Current page: 88 of 385
- Download datasheet (3Mb)
Lattice Semiconductor
DLL Timing
f
f
f
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1. CLKOP runs at the same frequency as the input clock.
2. CLKOS minimum frequency is obtained with divide by 4.
3. This is intended to be a “path-matching” design guideline and is not a measurable specification.
Timing v.A 0.11
Parameter
REF
FB
CLKOP
CLKOS
PJIT
CYJIT
DUTY
DUTYTRD
DUTYCIR
SKEW
PWH
PWL
R
INSTB
LOCK
RSWD
PA
RANGE1
RANGE4
, t
F
3
1
2
Input reference clock frequency (on-chip or off-chip)
Feedback clock frequency (on-chip or off-chip)
Output clock frequency, CLKOP
Output clock frequency, CLKOS
Output clock period jitter (clean input)
Output clock cycle to cycle jitter (clean input)
Output clock duty cycle (at 50% levels, 50% duty cycle input clock,
50% duty cycle circuit turned off, time reference delay mode)
Output clock duty cycle (at 50% levels, arbitrary duty cycle input
clock, 50% duty cycle circuit enabled, time reference delay mode)
Output clock duty cycle (at 50% levels, arbitrary duty cycle input
clock, 50% duty cycle circuit enabled, clock injection removal
mode)
Output clock to clock skew between two outputs with the same
phase setting
Input clock minimum pulse width high (at 80% level)
Input clock minimum pulse width low (at 20% level)
Input clock rise and fall time (20% to 80% levels)
Input clock period jitter
DLL lock time
Digital reset minimum pulse width (at 80% level)
Delay step size
Max. delay setting for single delay block (144 taps)
Max. delay setting for four chained delay blocks
Over Recommended Operating Conditions
Description
3-37
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
18,500
2.376
9.504
Min.
16.5
100
100
100
750
750
25
35
40
40
—
—
—
3
Typ.
42
24
—
—
—
—
—
—
—
—
—
—
—
—
6
34.214
+/-250
8.553
Max.
59.4
500
500
500
500
250
250
100
65
60
60
—
—
—
—
1
ps p-p
ps p-p
cycles
Units
MHz
MHz
MHz
MHz
ps
ps
ps
ns
ps
ns
ps
ns
ns
%
%
%
Related parts for LFE2-50E-5F484I
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
![LFE2-50E-5FN484C](/images/manufacturer_photos/0/3/381/lattice_semiconductor_tmb.jpg)
Part Number:
Description:
IC, LATTICEECP2 FPGA, 420MHZ, FPBGA-484
Manufacturer:
LATTICE SEMICONDUCTOR
Datasheet:
![LFE2-50E-H-EVN](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
Development Software Evaluation Board
Manufacturer:
Lattice
![LFE2-50E-VID-EV](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
Development Software LatticeECP2 Video Dev Kit
Manufacturer:
Lattice
Datasheet:
![LFE2-50E-D-EVN](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
MCU, MPU & DSP Development Tools LatticeMico32/DSP DEV BD/LatticeECP2
Manufacturer:
Lattice
Datasheet:
![LFE2-50E-H-EV](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
MCU, MPU & DSP Development Tools LatticeECP2 Eval Brd - Advanced
Manufacturer:
Lattice
Datasheet:
![LFE2-50E-L-EV](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
MCU, MPU & DSP Development Tools ECP-2 Standard Eval Board
Manufacturer:
Lattice
Datasheet:
![LFE2-50E-D-EV](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
MCU, MPU & DSP Development Tools LS Mico32/DSP Dev Br Brd for LS ECP2
Manufacturer:
Lattice
Datasheet:
![LFE2-50E-5F672C](/images/manufacturer_photos/0/3/381/lattice_semiconductor_tmb.jpg)
Part Number:
Description:
FPGA LatticeECP2 Family 48000 Cells 90nm (CMOS) Technology 1.2V 672-Pin FBGA
Manufacturer:
LATTICE SEMICONDUCTOR
Datasheet:
![LFE2-50E-5FN484I](/images/manufacturer_photos/0/3/381/lattice_semiconductor_tmb.jpg)
Part Number:
Description:
FPGA LatticeECP2 Family 48000 Cells 90nm (CMOS) Technology 1.2V 484-Pin FBGA
Manufacturer:
LATTICE SEMICONDUCTOR
Datasheet:
![LFE2-50E-5FN672C](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
IC FPGA 50KLUTS 500I/O 672-BGA
Manufacturer:
Lattice
Datasheet:
![LFE2-50E-6F484C](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
IC FPGA 50KLUTS 339I/O 484-BGA
Manufacturer:
Lattice
Datasheet:
![LFE2-50E-6FN484C](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
IC FPGA 50KLUTS 339I/O 484-BGA
Manufacturer:
Lattice
Datasheet:
![LFE2-50E-7FN484C](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
IC FPGA 50KLUTS 339I/O 484-BGA
Manufacturer:
Lattice
Datasheet:
![LFE2-50E-7FN672C](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
IC FPGA 50KLUTS 500I/O 672-BGA
Manufacturer:
Lattice
Datasheet:
![LFE2-50E-6FN672C](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
IC FPGA 48KLUTS 672FPBGA
Manufacturer:
Lattice
Datasheet: