LFE2-50E-5F484I Lattice, LFE2-50E-5F484I Datasheet - Page 128
![no-image](/images/manufacturer_photos/0/3/380/lattice_sml.jpg)
LFE2-50E-5F484I
Manufacturer Part Number
LFE2-50E-5F484I
Description
FPGA 48000 CELLS 90NM (CMOS) 1.2
Manufacturer
Lattice
Series
ECP2r
Datasheet
1.LFE2-12E-5FN256C.pdf
(385 pages)
Specifications of LFE2-50E-5F484I
Number Of Logic Elements/cells
48000
Number Of Labs/clbs
6000
Total Ram Bits
396288
Number Of I /o
339
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-BBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q3220905AABC
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Lattice Semiconductor
LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 208 PQFP (Cont.)
Number
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
Pin
92
93
94
95
96
97
98
99
RLM0_PLLCAP
PROGRAMN
Function
VCCAUX
VCCIO4
VCCIO4
VCCIO8
VCCIO8
VCCIO3
VCCIO3
Pin/Pad
PB44A
PB44B
PB48A
PB48B
PB52A
PB52B
PB54A
PB55A
PB55B
PR29A
PR26A
PR25B
PR25A
PR24B
PR24A
PR21A
PR20B
PR20A
PR18B
PR18A
PR17B
PR17A
PR16B
PR16A
PR15B
DONE
CFG1
CFG2
CFG0
CCLK
INITN
GND
GND
GND
VCC
VCC
VCC
Bank
LFE2-12E/SE
4
4
4
4
4
4
4
4
4
4
4
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
3
3
3
3
3
3
3
3
3
3
3
3
3
-
-
-
-
-
-
-
RLM0_GDLLC_IN_A**
RLM0_GPLLC_IN_A**
RLM0_GPLLT_IN_A**
RLM0_GDLLT_IN_A**
RLM0_GDLLC_FB_A
RLM0_GDLLT_FB_A
RLM0_GPLLT_FB_A
VREF2_4/BDQ51
VREF1_4/BDQ51
D0/SPIFASTN
DOUT/CSON
DI/CSSPI0N
BUSY/SISPI
PCLKC3_0
Function
VREF2_3
VREF1_3
BDQ42
BDQ42
BDQ51
BDQ51
BDQ51
BDQ51
BDQ51
Dual
D6
D7
Differential
C (LVDS)*
C (LVDS)*
C (LVDS)*
T (LVDS)*
T (LVDS)*
C
C
C
C
C
C
C
C
T
T
T
T
T
T
T
T
4-28
RLM0_PLLCAP
PROGRAMN
Function
VCCAUX
VCCIO4
VCCIO4
VCCIO8
VCCIO8
VCCIO3
VCCIO3
Pin/Pad
PB54A
PB54B
PB58A
PB58B
PB60A
PB60B
PB63A
PB64A
PB64B
PR43A
PR40A
PR39B
PR39A
PR38B
PR38A
PR31A
PR30B
PR30A
PR28B
PR28A
PR27B
PR27A
PR22B
PR22A
PR21B
DONE
CFG1
CFG2
CFG0
CCLK
INITN
GND
GND
GND
VCC
VCC
VCC
LatticeECP2/M Family Data Sheet
Bank
4
4
4
4
4
4
4
4
4
4
4
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
3
3
3
3
3
3
3
3
3
3
3
3
3
-
-
-
-
-
-
-
RLM0_GDLLT_FB_A**/RDQ25
RLM0_GPLLC_IN_A**/RDQ34
RLM0_GDLLT_IN_A**/RDQ25
RLM0_GPLLT_IN_A**/RDQ34
RLM0_GDLLC_FB_A/RDQ25
RLM0_GPLLT_FB_A/RDQ34
RLM0_GDLLC_IN_A/RDQ25
LFE2-20E/SE
PCLKC3_0/RDQ25
VREF2_3/RDQ25
VREF1_3/RDQ25
VREF2_4/BDQ60
VREF1_4/BDQ60
D0/SPIFASTN
DOUT/CSON
DI/CSSPI0N
BUSY/SISPI
Function
BDQS60
BDQ51
BDQ51
BDQ60
BDQ60
BDQ60
BDQ60
Dual
D6
D7
Pinout Information
Differential
C (LVDS)*
C (LVDS)*
C (LVDS)*
T (LVDS)*
T (LVDS)*
C
C
C
C
C
C
C
C
T
T
T
T
T
T
T
T
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