LFE2-50E-5F484I Lattice, LFE2-50E-5F484I Datasheet - Page 34

• Manufacturer Part Number: LFE2-50E-5F484I
• Description: FPGA 48000 CELLS 90NM (CMOS) 1.2
• Manufacturer: Lattice
• Series: ECP2r

Specifications of LFE2-50E-5F484I

• Number Of Logic Elements/cells: 48000
• Number Of Labs/clbs: 6000
• Total Ram Bits: 396288
• Number Of I /o: 339
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-BBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q3220905AABC

Lattice Semiconductor
By combining input blocks of the complementary PIOs and sharing some registers from output blocks, a gearbox
function can be implemented, which takes a double data rate signal applied to PIOA and converts it as four data
streams, IPOS0A, IPOS1A, IPOS0B and IPOS1B. Figure 2-29 shows the diagram using this gearbox function. For
more information about this topic, please see information regarding additional documentation at the end of this
data sheet.
The signal DDRCLKPOL controls the polarity of the clock used in the synchronization registers. It ensures ade-
quate timing when data is transferred from the DQS to the system clock domain. For further information about this
topic, see the DDR Memory section of this data sheet.
Figure 2-29. Input Register Block for Left, Right and Bottom Edges
CLK0 (of PIO B)
CLK0 (of PIO A)
DDRCLKPOL
DDRCLKPOL
(From sysIO
(From sysIO
Routing
Routing
DEL [3:0]
From
From
Buffer)
Buffer)
DEL [3:0]
Delayed
Delayed
DI
DI
DQS
DQS
CLKA
CLKB
*Shared with output register
**Selected PIO.
True PIO (A) in LVDS I/O Pair
Comp PIO (B) in LVDS I/O Pair
Dynamic Delay
Dynamic Delay
Fixed Delay
Fixed Delay
0
1
0
1
0
1
0
1
DDR Registers
DDR Registers
D
D
D
D
D-Type
D-Type
D-Type
D-Type
Q
Q
Q
Q
D1
D1
0
1
D
D
D-Type
DDRSRC
D-Type
D0
0
1
Q
Q
2-31
Gearbox Configuration Bit
D2
D0
D2
0
1
0
1
SDR & Sync
SDR & Sync
Registers
Registers
D
D
D
D
/LATCH
/LATCH
/LATCH
/LATCH
D-Type
D-Type
D-Type
D-Type
LatticeECP2/M Family Data Sheet
Q
Q
Q
Q
Note: Simplified version does not
show CE and SET/RESET details
Clock Transfer Registers
Clock Transfer Registers
D
D
D
D
D-Type*
D-Type*
D-Type*
D-Type*
Q
Q
Q
Q
INCK**
To DQS Delay Block**
INDD
IPOS0A
QPOS0A
IPOS1A
QPOS1A
INCK**
To DQS Delay Block**
INDD
IPOS0B
QPOS0B
IPOS1B
QPOS1B
Architecture
Routing
Routing
To
To