LFE2-50E-5F484I Lattice, LFE2-50E-5F484I Datasheet - Page 305
![no-image](/images/manufacturer_photos/0/3/380/lattice_sml.jpg)
LFE2-50E-5F484I
Manufacturer Part Number
LFE2-50E-5F484I
Description
FPGA 48000 CELLS 90NM (CMOS) 1.2
Manufacturer
Lattice
Series
ECP2r
Datasheet
1.LFE2-12E-5FN256C.pdf
(385 pages)
Specifications of LFE2-50E-5F484I
Number Of Logic Elements/cells
48000
Number Of Labs/clbs
6000
Total Ram Bits
396288
Number Of I /o
339
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-BBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q3220905AABC
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LFE2M50E/SE and LFE2M70E/SE Logic Signal Connections: 900 fpBGA
Lattice Semiconductor
Number
* Supports true LVDS. Other differential signals must be emulated with external resistors.
** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant.
*** These sysCONFIG pins are dedicated I/O pins for configuration. The outpus are actively driven during normal device operation.
****Due to packaging bond out option, this DQS does not have all the necessary DQ pins bonded out for a full 8-bit data width.
Note: VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the
last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one to one con-
nection with a package ball or pin.
Ball
U22
N13
N18
V13
V18
J10
J20
J21
W9
R9
K9
J9
Function
Ball/Pad
VCCPLL
VCCPLL
VCCPLL
VCCPLL
PL2B
PL4A
PL4B
NC
NC
NC
NC
NC
LFE2M50E/SE
Bank
7
7
7
-
-
-
-
-
-
-
-
-
Dual Function
LDQ6
LDQ6
LDQ6
Differential
C (LVDS)*
C (LVDS)*
T (LVDS)*
4-205
Function
Ball/Pad
VCCPLL
VCCPLL
VCCPLL
VCCPLL
NC
NC
NC
NC
NC
NC
NC
NC
LatticeECP2/M Family Data Sheet
Bank
-
-
-
-
-
-
-
-
-
-
-
-
LFE2M70E/SE
Dual Function
Pinout Information
Differential
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