LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 28
LPC1810FET100,551
Manufacturer Part Number
LPC1810FET100,551
Description
IC MCU 32BIT 136KB FLSH 100TFBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1810FET100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
64
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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User manual
3.3.4.2 UART boot mode
Figure 11
happens only if the boot mode is set accordingly (see boot modes
As illustrated in
Auto baud is active; boot waits until 0x3F is received and responds with “OK”. This should
be followed by the header and image. The boot ROM doesn't implement any flow control
or any handshake mechanisms during file transfer.
Fig 10. CMAC generation
•
•
•
•
Baudrate = 115200 (UART divisor registers are programmed assuming a 12 MHz
clock frequency).
Data bits = 8.
Parity = None.
Stop bits = 1.
details the boot-flow steps of the UART boot mode. The execution of this mode
AES
All information provided in this document is subject to legal disclaimers.
Figure
M
1
K
Rev. 00.13 — 20 July 2011
11, configure the UART with the following settings:
AES
M
+
2
K
AES
M*
+
n
K
K
Chapter 3: LPC18xx Boot ROM
1
MSB
64
Table 7
UM10430
© NXP B.V. 2011. All rights reserved.
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Table
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