LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 635

• Manufacturer Part Number: LPC1810FET100,551
• Description: IC MCU 32BIT 136KB FLSH 100TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1810FET100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Size: -
• Program Memory Type: ROMless
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

26.1 How to read this chapter
26.2 Basic configuration
26.3 Introduction
26.4 Features
26.5 General description
<Document ID>
User manual
The Motor control PWM is available on all LPC18xx parts.
The PWM is configured as follows:
Table 546. PWM clocking and power control
The Motor Control PWM (MCPWM) is optimized for three-phase AC and DC motor control
applications, but can be used in many other applications that need timing, counting,
capture, and comparison.
The MCPWM contains three independent channels, each including:
Input pins MCI0-2 can trigger TC capture or increment a channel’s TC. A global Abort
input can force all of the channels into “A passive” state and cause an interrupt.
Section 26.8
but a quick preview here will provide background for the register descriptions below.
Clock to the PWM Motor control block and
PWM Motocon peripheral clock.
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UM10430
Chapter 26: LPC18xx Motor Control PWM (MOTOCONPWM)
Rev. 00.13 — 20 July 2011
See
The PWM is reset by the MOTOCONPWM_RST (reset #38).
The PWM interrupt is connected to slot # 16 in the NVIC.
a 32-bit Timer/Counter (TC)
a 32-bit Limit register (LIM)
a 32-bit Match register (MAT)
a 10-bit dead-time register (DT) and an associated 10-bit dead-time counter
a 32-bit capture register (CAP)
two modulated outputs (MCOA and MCOB) with opposite polarities
a period interrupt, a pulse-width interrupt, and a capture interrupt
Table 546
includes detailed descriptions of the various modes of MCPWM operation,
All information provided in this document is subject to legal disclaimers.
for clocking and power control.
Rev. 00.13 — 20 July 2011
Base clock
BASE_APB1_
CLK
Branch clock
CLK_APB1_
MOTOCON
© NXP B.V. 2011. All rights reserved.
User manual
Maximum
frequency
150 MHz
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