LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 463
LPC1810FET100,551
Manufacturer Part Number
LPC1810FET100,551
Description
IC MCU 32BIT 136KB FLSH 100TFBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1810FET100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
64
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Table 388. Port Status and Control register in device mode (PORTSC1_D - address 0x4000 7184) bit description
<Document ID>
User manual
Bit
19:16 PTC3_0
20
21
22
23
24
25
27:26 PSPD
29:28 -
31:30 PTS
Symbol
-
-
-
PHCD
PFSC
-
Value Description
0x0
0x1
0x2
0x3
0x4
0x5
0x6
-
-
0
1
0
1
-
0x1
0x2
0x3
-
0x2
0x3
Port test control
J_STATE
K_STATE
PHY low power suspend - clock disable (PLPSCD)
Port force full speed connect
Reserved
Port speed
Serial/ 1.1 PHY (Full-speed only)
Any value other than 0000 indicates that the port is operating in test mode.
The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the
test mode support specified in the EHCI specification. Writing the PTC field
to any of the FORCE_ENABLE_HS/FS/LS values will force the port into
the connected and enabled state at the selected speed. Writing the PTC
field back to TEST_MODE_DISABLE will allow the port state machines to
progress normally from that point. Values 0x7 to 0xF are reserved.
TEST_MODE_DISABLE
SE0 (host)/NAK (device)
Packet
FORCE_ENABLE_HS
FORCE_ENABLE_FS
Not used in device mode. This bit is always 0 in device mode.
Not used in device mode. This bit is always 0 in device mode.
Not used in device mode. This bit is always 0 in device mode.
In device mode, The PHY can be put into Low Power Suspend – Clock
Disable when the device is not running (USBCMD Run/Stop = 0) or the
host has signaled suspend (PORTSC SUSPEND = 1). Low power suspend
will be cleared automatically when the host has signaled resume. Before
forcing a resume from the device, the device controller driver must clear
this bit.
Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the
PHY clock (enabled).
Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the
PHY clock (disabled).
Port connects at any speed.
Writing this bit to a 1 will force the port to only connect at full speed. It
disables the chirp sequence that allows the port to identify itself as
High-speed. This is useful for testing FS configurations with a HS host, hub
or device.
This register field indicates the speed at which the port is operating.
Full-speed
invalid in device mode
High-speed
Reserved
Parallel transceiver select. All other values are reserved.
ULPI
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 21: LPC18xx USB1 Host/Device controller
UM10430
0
0
0
<tbd>
Reset
value
0000
0
0
0
-
© NXP B.V. 2011. All rights reserved.
463 of 1164
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-
-
R/W
R/W
Access
R/W
R/W
RO
-
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