LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 954

• Manufacturer Part Number: LPC1810FET100,551
• Description: IC MCU 32BIT 136KB FLSH 100TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1810FET100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Size: -
• Program Memory Type: ROMless
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NXP Semiconductors
<Document ID>
User manual
42.1.8.8 Interrupt Priority Register 2
42.1.8.9 Interrupt Priority Register 3
Table 893. Interrupt Priority Register 1 (IPR1 - address 0xE000 E404) bit
The IPR2 register controls the priority of the third group of 4 peripheral interrupts. Each
interrupt can have one of 32 priorities, where 0 is the highest priority.
Table 894. Interrupt Priority Register 2 (IPR2 - address 0xE000 E408) bit
The IPR3 register controls the priority of the fourth group of 4 peripheral interrupts. Each
interrupt can have one of 32 priorities, where 0 is the highest priority.
Table 895. Interrupt Priority Register 3 (IPR3 - address 0xE000 E40C) bit
Bit
23:19 IP_SDIO
26:24 -
31:27 IP_LCD
Bit
2:0
7:3
10:8
15:11 IP_USB1
18:16 -
23:19 IP_SCT
26:24 -
31:27 IP_RIT
Bit
2:0
7:3
10:8
15:11 IP_TIMER1 TIMER1 interrupt priority. 0 = highest priority. 31 (0x1F) = lowest
18:16 -
23:19 IP_TIMER2 TIMER2 interrupt priority. 0 = highest priority. 31 (0x1F) = lowest
26:24 -
31:27 IP_TIMER3 TIMER3 interrupt priority. 0 = highest priority. 31 (0x1F) = lowest
Symbol
Symbol
-
IP_USB0
-
Symbol
-
IP_TIMER0 TIMER0 interrupt priority. 0 = highest priority. 31 (0x1F) = lowest
-
description
description
description
All information provided in this document is subject to legal disclaimers.
USB0 interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority. 0
USB1 interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority. 0
Description
Reserved.These bits ignore writes, and read as 0.
Reserved.These bits ignore writes, and read as 0.
Reserved.These bits ignore writes, and read as 0.
SCT interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority.
Reserved.These bits ignore writes, and read as 0.
RIT interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority.
Description
SDIO interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority. 0
Reserved.These bits ignore writes, and read as 0.
LCD interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority.
Description
Reserved.These bits ignore writes, and read as 0.
priority.
Reserved.These bits ignore writes, and read as 0.
priority.
Reserved.These bits ignore writes, and read as 0.
priority.
Reserved.These bits ignore writes, and read as 0.
priority.
…continued
Rev. 00.13 — 20 July 2011
Chapter 42: Appendix
UM10430
© NXP B.V. 2011. All rights reserved.
954 of 1164
Reset
value
0
0
0
0
0
0
0
0
Reset
value
0
0
0
0
0
0
Reset
value
0
0