LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 631
LPC1810FET100,551
Manufacturer Part Number
LPC1810FET100,551
Description
IC MCU 32BIT 136KB FLSH 100TFBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1810FET100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
64
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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25.7.11 Timer count control registers
Table 543. Timer external match registers (EMR - addresses 0x4008 403C (TIMER0),
Table 544. External Match Control
The Count Control Register (CTCR) is used to select between Timer and Counter mode,
and in Counter mode to select the pin and edge(s) for counting.
When Counter Mode is chosen as a mode of operation, the CAP input (selected by the
CTCR bits 3:2) is sampled on every rising edge of the PCLK clock. After comparing two
consecutive samples of this CAP input, one of the following four events is recognized:
rising edge, falling edge, either of edges or no changes in the level of the selected CAP
input. Only if the identified event corresponds to the one selected by bits 1:0 in the CTCR
register, the Timer Counter register will be incremented.
Effective processing of the externally supplied clock to the counter has some limitations.
Since two successive rising edges of the PCLK clock are used to identify only one edge
on the CAP selected input, the frequency of the CAP input can not exceed one quarter of
the PCLK clock. Consequently, duration of the high/low levels on the same CAP input in
this case can not be shorter than 1/(2 PCLK).
Bit
11:10 EMC3
15:12 -
EMR[11:10], EMR[9:8],
EMR[7:6], or EMR[5:4]
Symbol Value
0x4008 503C (TIMER1), 0x400C 303C (TIMER2), 0x400C 403C (TIMER3)) bit
description
00
01
10
11
All information provided in this document is subject to legal disclaimers.
0x0
0x1
0x2
0x3
Rev. 00.13 — 20 July 2011
Description
External Match 3.
Do Nothing.
Clear the corresponding External Match bit/output to 0
(MATn.m pin is LOW if pinned out).
Set the corresponding External Match bit/output to 1 (MATn.m
pin is HIGH if pinned out).
Toggle the corresponding External Match bit/output.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
External Match Control 3. Determines the functionality of
Function
Do Nothing.
Clear the corresponding External Match bit/output to 0 (MATn.m pin is
LOW if pinned out).
Set the corresponding External Match bit/output to 1 (MATn.m pin is
HIGH if pinned out).
Toggle the corresponding External Match bit/output.
Chapter 25: LPC18xx Timer0/1/2/3
UM10430
© NXP B.V. 2011. All rights reserved.
631 of 1164
Reset
value
00
NA
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