LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 5
LPC1810FET100,551
Manufacturer Part Number
LPC1810FET100,551
Description
IC MCU 32BIT 136KB FLSH 100TFBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1810FET100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
64
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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User manual
•
•
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– Two 32 kB SRAM blocks with separate bus access. Both SRAM blocks can be
– 64 kB ROM containing boot code and on-chip software drivers.
– 32-bit One-Time Programmable (OTP) memory for general-purpose customer use.
On-chip memory (parts with on-chip flash)
– Up to 1 MB total dual bank flash memory with flash accelerator.
– In-System Programming (ISP) and In-Application Programming (IAP) via on-chip
– Up to 136 kB SRAM for code and data use.
– Two 32 kB SRAM blocks with separate bus access. Both SRAM blocks can be
– 32 kB ROM containing boot code and on-chip software drivers.
– 32-bit One-Time Programmable (OTP) memory for general-purpose customer use.
Clock generation unit
– Crystal oscillator with an operating range of 1 MHz to 25 MHz.
– 12 MHz internal RC oscillator trimmed to 1 % accuracy.
– Ultra-low power RTC crystal oscillator.
– Three PLLs allow CPU operation up to the maximum CPU rate without the need for
– Clock output.
Serial interfaces:
– Quad SPI Flash Interface (SPIFI) with four lanes and data rates of up to 40 MB per
– 10/100T Ethernet MAC with RMII and MII interfaces and DMA support for high
– One High-speed USB 2.0 Host/Device/OTG interface with DMA support and
– One High-speed USB 2.0 Host/Device interface with DMA support, on-chip
– USB interface electrical test software included in ROM USB stack.
– Four 550 UARTs with DMA support: one UART with full modem interface; one
– Two C_CAN 2.0B controllers with one channel each.
– Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMA
– One Fast-mode Plus I
– One standard I
powered down individually.
bootloader software.
powered down individually.
a high-frequency crystal. The second PLL is dedicated to the High-speed USB, the
third PLL can be used as audio PLL.
second total.
throughput at low CPU load. Support for IEEE 1588 time stamping/advanced time
stamping (IEEE 1588-2008 v2).
on-chip PHY.
full-speed PHY and ULPI interface to external high-speed PHY.
UART with IrDA interface; three USARTs support synchronous mode and a smart
card interface conforming to ISO7816 specification.
support.
pins conforming to the full I
1 Mbit/s.
All information provided in this document is subject to legal disclaimers.
2
Rev. 00.13 — 20 July 2011
C-bus interface with monitor mode and standard I/O pins.
2
C-bus interface with monitor mode and with open-drain I/O
2
C-bus specification. Supports data rates of up to
Chapter 1: Introductory information
UM10430
© NXP B.V. 2011. All rights reserved.
5 of 1164
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