LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 540
LPC1810FET100,551
Manufacturer Part Number
LPC1810FET100,551
Description
IC MCU 32BIT 136KB FLSH 100TFBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1810FET100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
64
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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23.1 How to read this chapter
23.2 Basic configuration
23.3 Features
<Document ID>
User manual
The LCD controller is available on part LPC1850.
The LCD controller is configured as follows:
Table 450. LCD clocking and power control
LCD register
interface clock
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UM10430
Chapter 23: LPC18xx LCD
Rev. 00.13 — 20 July 2011
See
The LCD is reset by the LCD_RST (reset # 16).
The LCD interrupt is connected to interrupt slot # 7 in the NVIC.
AHB bus master interface to access frame buffer.
Setup and control via a separate AHB slave interface.
Dual 16-deep programmable 64-bit wide FIFOs for buffering incoming display data.
Supports single and dual-panel monochrome Super Twisted Nematic (STN) displays
with 4 or 8-bit interfaces.
Supports single and dual-panel color STN displays.
Supports Thin Film Transistor (TFT) color displays.
Programmable display resolution including, but not limited to: 320x200, 320x240,
640x200, 640x240, 640x480, 800x600, and 1024x768.
Hardware cursor support for single-panel displays.
15 gray-level monochrome, 3375 color STN, and 32K color palettized TFT support.
1, 2, or 4 bits-per-pixel (bpp) palettized displays for monochrome STN.
1, 2, 4, or 8 bpp palettized color displays for color STN and TFT.
16 bpp true-color non-palettized, for color STN and TFT.
24 bpp true-color non-palettized, for color TFT.
Programmable timing for different display panels.
256 entry, 16-bit palette RAM, arranged as a 128x32-bit RAM.
Frame, line, and pixel clock signals.
AC bias signal for STN, data enable signal for TFT panels.
Supports little and big-endian, and Windows CE data formats.
Table 450
All information provided in this document is subject to legal disclaimers.
Base clock
BASE_M3_CLK
for clocking and power control.
Rev. 00.13 — 20 July 2011
Branch clock
CLK_M3_LCD
Maximum
frequency
150 MHz
Notes
-
© NXP B.V. 2011. All rights reserved.
User manual
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