NUC130LE3CN Nuvoton Technology Corporation of America, NUC130LE3CN Datasheet - Page 139

• Manufacturer Part Number: NUC130LE3CN
• Description: IC MCU 32BIT 128KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™ NUC100r

Specifications of NUC130LE3CN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Clock status Register (CLKSTATUS)
These bits of this register are used to monitor if the chip clock source stable or not, and whether
clock switch failed.
Register
CLKSTATUS CLK_BA+0x0C
CLK_SW_FAI
Bits
[31:8]
[7]
[6:5]
[4]
[3]
[2]
31
23
15
7
L
NuMicro™ NUC130/NUC140 Technical Reference Manual
Offset
Descriptions
Reserved
CLK_SW_FAIL
Reserved
OSC22M_STB
OSC10K_STB
PLL_STB
30
22
14
6
Reserved
R/W
R/W
Reserved
Clock Switching Fail Flag (write-protection bit)
1 = Clock switching failure
0 = Clock switching success
This bit is updated when software switches system clock source. If switch target clock
is stable, this bit will be set to 0. If switch target clock is not stable, this bit will be set to
1.
Write 1 to clear the bit to zero.
Reserved
Internal 22.1184 MHz High Speed Oscillator Clock Source Stable Flag
1 = Internal 22.1184 MHz high speed oscillator clock is stable
0 = Internal 22.1184 MHz high speed oscillator clock is not stable or disabled
This is read only bit
Internal 10 kHz Low Speed Oscillator Clock Source Stable Flag
1 = Internal 10 kHz low speed oscillator clock is stable
0 = Internal 10 kHz low speed oscillator clock is not stable or disabled
This is read only bit
Internal PLL Clock Source Stable Flag
1 = Internal PLL clock is stable
0 = Internal PLL clock is not stable or disabled
This is read only bit
29
21
13
5
Description
Clock status monitor Register
OSC22M_ST
28
20
12
B
4
- 139 -
Reserved
Reserved
Reserved
OSC10K_ST
27
19
11
B
3
Publication Release Date: June 14, 2011
PLL_STB
26
18
10
2
XTL32K_STB XTL12M_STB
25
17
9
1
Revision V2.01
Reset Value
0x0000_00XX
24
16
8
0